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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
NASA NTRS1977

Effect of virtual memory on efficient solution of two model problems

Computers with virtual memory architecture allow programs to be written as if they were small enough to be contained in memory. Two types of problems are investigated to show that this luxury can lead to quite an inefficient performance if the programmer does not interact strongly with the characteristics of the operating system when developing the program. The two problems considered are the simultaneous solutions of a large linear system of equations by Gaussian elimination and a model three-dimensional finite-difference problem. The Control Data STAR-100 computer runs are made to demonstrate the inefficiencies of programming the problems in the manner one would naturally do if the problems were indeed, small enough to be contained in memory. Program redesigns are presented which achieve large improvements in performance through changes in the computational procedure and the data base arrangement.

Lambiotte, J. J., Jr.↗
NASA NTRS1977

Memory device for two-dimensional radiant energy array computers

A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

Schaefer, D. H.↗
NASA NTRS1979

Optical memories in digital computing

High capacity optical memories with relatively-high data-transfer rate and multiport simultaneous access capability may serve as basis for new computer architectures. Several computer structures that might profitably use memories are: a) simultaneous record-access system, b) simultaneously-shared memory computer system, and c) parallel digital processing structure.

Alford, C. O.↗
NASA NTRS1979

Some optimal partial-unit-memory codes

A class of time-invariant binary convolutional codes is defined, called partial-unit-memory codes. These codes are optimal in the sense of having maximum free distance for given values of R, k (the number of encoder inputs), and mu (the number of encoder memory cells). Optimal codes are given for rates R = 1/4, 1/3, 1/2, and 2/3, with mu not greater than 4 and k not greater than mu + 3, whenever such a code is better than previously known codes. An infinite class of optimal partial-unit-memory codes is also constructed based on equidistant block codes.

Lauer, G. S.↗
NASA NTRS1979

Memory effects in turbulence

Experimental investigations of the wake flow of a hemisphere and cylinder show that such memory effects can be substantial and have a significant influence on momentum transport. Memory effects are described in terms of suitable memory functions.

Hinze, J. O.↗
NASA NTRS1980

Flight software memory sizing and CPU loading estimates

Estimates of the AP101 memory and central processing unit (CPU) requirements for the space shuttle orbiter are presented. The resource estimates reflect OASCAB approved change requests for Release 18 and Release 19. Memory sizes are presented in 32 bit full words, CPU loading is listed by percentage. Memory and CPU information was obtained from actual AP101 code where available, and from estimates provided by flight software development programmers.

Source record↗
NASA NTRS1979

Cosmic ray-induced soft errors in static MOS memory cells

Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against cosmic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are in general agreement with previous spacecraft flight data.

Sivo, L. L.↗
NASA NTRS1981

Memory-based frame synchronizer

A frame synchronizer for use in digital communications systems wherein data formats can be easily and dynamically changed is described. The use of memory array elements provide increased flexibility in format selection and sync word selection in addition to real time reconfiguration ability. The frame synchronizer comprises a serial-to-parallel converter which converts a serial input data stream to a constantly changing parallel data output. This parallel data output is supplied to programmable sync word recognizers each consisting of a multiplexer and a random access memory (RAM). The multiplexer is connected to both the parallel data output and an address bus which may be connected to a microprocessor or computer for purposes of programming the sync word recognizer. The RAM is used as an associative memory or decorder and is programmed to identify a specific sync word. Additional programmable RAMs are used as counter decoders to define word bit length, frame word length, and paragraph frame length.

Stattel, R. J.↗
NASA NTRS1984

Transfer Function Bounds for Partial-unit-memory Convolutional Codes Based on Reduced State Diagram

The performance of a coding system consisting of a convolutional encoder and a Viterbi decoder is analytically found by the well-known transfer function bounding technique. For the partial-unit-memory byte-oriented convolutional encoder with m sub 0 binary memory cells and (k sub 0 m sub 0) inputs, a state diagram of 2(K) (sub 0) was for the transfer function bound. A reduced state diagram of (2 (m sub 0) +1) is used for easy evaluation of transfer function bounds for partial-unit-memory codes.

Lee, P. J.↗
NASA NTRS1984

Reed Solomon codes for error control in byte organized computer memory systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

Lin, S.↗
NASA NTRS1985

Low-Voltage Protection For Volatile Computer Memories

Short-circuit current provides minimum memory power. Protective circuit includes dc-to-dc converter that supplies keep-alive voltage to memories when short circuit occurs in any of system loads. Converter powered by lowvoltage across two of three series diodes generated by short-circuit bus current. Relay switch is in open (short-circuit-detected) position. Protective circuit useful wherever necessary to improve reliability of volatile memories or other circuits that must not lose power.

Detwiler, R. C.↗
NASA NTRS1986

Improved memory loading techniques for the TSRV display system

A recent upgrade of the TSRV research flight system at NASA Langley Research Center retained the original monochrome display system. However, the display memory loading equipment was replaced requiring design and development of new methods of performing this task. This paper describes the new techniques developed to load memory in the display system. An outdated paper tape method for loading the BOOTSTRAP control program was replaced by EPROM storage of the characters contained on the tape. Rather than move a tape past an optical reader, a counter was implemented which steps sequentially through EPROM addresses and presents the same data to the loader circuitry. A cumbersome cassette tape method for loading the applications software was replaced with a floppy disk method using a microprocessor terminal installed as part of the upgrade. The cassette memory image was transferred to disk and a specific software loader was written for the terminal which duplicates the function of the cassette loader.

Easley, W. C.↗
NASA NTRS1986

Virtual memory

Virtual memory was conceived as a way to automate overlaying of program segments. Modern computers have very large main memories, but need automatic solutions to the relocation and protection problems. Virtual memory serves this need as well and is thus useful in computers of all sizes. The history of the idea is traced, showing how it has become a widespread, little noticed feature of computers today.

Denning, P. J.↗
NASA NTRS1985

Electronic device aspects of neural network memories

The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

Lambe, J.↗
NASA NTRS1986

Fault latency in the memory - An experimental study on VAX 11/780

Fault latency is the time between the physical occurrence of a fault and its corruption of data, causing an error. The measure of this time is difficult to obtain because the time of occurrence of a fault and the exact moment of generation of an error are not known. This paper describes an experiment to accurately study the fault latency in the memory subsystem. The experiment employs real memory data from a VAX 11/780 at the University of Illinois. Fault latency distributions are generated for s-a-0 and s-a-1 permanent fault models. Results show that the mean fault latency of a s-a-0 fault is nearly 5 times that of the s-a-1 fault. Large variations in fault latency are found for different regions in memory. An analysis of a variance model to quantify the relative influence of various workload measures on the evaluated latency is also given.

Chillarege, Ram↗
NASA NTRS1987

The impact of domain partitioning on the performance of a shared memory multiprocessor

The impact of the choice of domain partition/stencil pairs in solving elliptic partial differential equations on a multiprocessor system with both global shared memory and local memory is considered. A parallel execution time model is given for square and hexagonal partitions using both five-point and nine-point star discretizations. Results from the model for a particular multiprocessor system show that keeping copies of partition boundaries in local memory significantly improves performance.

Patrick, Merrell L.↗
NASA NTRS1988

Shape memory alloys: New materials for future engineering

Shape memory is a new material property. An alloy which experiences relative severe plastic deformation resumes its original shape again after heating by 10 to 100 C. Besides simple shape memory, in similar alloys there is the second effect where the change in shape is caused exclusively by little temperature change. In pseudo-elasticity, the alloy exhibits a rubber-like behavior, i.e., large, reversible deformation at little change in tension. Beta Cu and beta NiTi alloys have been used in practice. The probability is that soon alloys based on Fe will become available. Recently increasing applications for this alloy were found in various areas of technology, even medical technology. A review with 24 references is given, including properties, production, applications and fundamental principles of the shape memory effect.

Hornbogen, E.↗
NASA NTRS1987

Binary synaptic connections based on memory switching in a-Si:H for artificial neural networks

A scheme for nonvolatile associative electronic memory storage with high information storage density is proposed which is based on neural network models and which uses a matrix of two-terminal passive interconnections (synapses). It is noted that the massive parallelism in the architecture would require the ON state of a synaptic connection to be unusually weak (highly resistive). Memory switching using a-Si:H along with ballast resistors patterned from amorphous Ge-metal alloys is investigated for a binary programmable read only memory matrix. The fabrication of a 1600 synapse test array of uniform connection strengths and a-Si:H switching elements is discussed.

Thakoor, A. P.↗