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At least 307 records · Page 17

Self-Security for Grid-Interactive Smart Inverters Using Steady-State Reference Model

Smart inverters exchange information with other devices through a shared communication link, making the inverters more prone to receive harmful commands from external parties. This erroneous data can be received due to an anomaly in the system, such as a device fault, unintentional utility operator action, or a cyber-attack. In this paper, a device-level self-security strategy is implemented using reference models for a grid-interactive inverter to examine the incoming power setpoints, detect the anomalies, and protect the system accordingly. The PQ setpoints received from the utility supervisory controller are autonomously examined using the inverter’s normal and stable operating regions before engaging the setpoints to the inverter’s local controller. Grid parameters are estimated in real-time during the examination process. The efficacy of the self-security algorithm is tested using a three-phase 3-kVA SiC-MOSFET inverter and a 12-kW NHR 9410 regenerative grid emulator. The results verify that the proposed method can detect harmful PQ setpoints that can cause abnormal or unstable inverter operation.

Gursoy, Mehmetcan↗

Silicon carbide, a semiconductor for space power electronics

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Powell, J. Anthony↗

Silicon carbide, a semiconductor for space power electronics

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the area of crystal growth and device fabrication technology. High quality of single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Powell, J. A.↗

Power conditioning for large dc motors for space flight applications

The design and performance of a prototype power-conditioning system for use with large brushless dc motors on NASA space missions are discussed in detail and illustrated with extensive diagrams, drawings, and graphs. The 5-kW 8-phase parallel module evaluated here would be suitable for use in the Space Shuttle Orbiter cargo bay. A current-balancing magnetic assembly with low distributed inductance permits high-speed current switching from a low-voltage bus as well as current balancing between parallel MOSFETs.

Veatch, Martin S.↗

Hardware in the Loop Testing of an Iodine-Fed Hall Thruster

CUBESATS are relatively new spacecraft platforms that are typically deployed from a launch vehicle as a secondary payload,1 providing low-cost access to space for a wide range of end-users. These satellites are comprised of building blocks having dimensions of 10x10x10 cm cu and a mass of 1.33 kg (a 1-U size). While providing low-cost access to space, a major operational limitation is the lack of a propulsion system that can fit within a CubeSat and is capable of executing high delta v maneuvers. This makes it difficult to use CubeSats on missions requiring certain types of maneuvers (i.e. formation flying, spacecraft rendezvous). Recently, work has been performed investigating the use of iodine as a propellant for Hall-effect thrusters (HETs) 2 that could subsequently be used to provide a high specific impulse path to CubeSat propulsion. Iodine stores as a dense solid at very low pressures, making it acceptable as a propellant on a secondary payload. It has exceptionally high ρIsp (density times specific impulse), making it an enabling technology for small satellite near-term applications and providing the potential for systems-level advantages over mid-term high power electric propulsion options. Iodine flow can also be thermally regulated, subliming at relatively low temperature ( less than100 C) to yield I2 vapor at or below 50 torr. At low power, the measured performance of an iodine-fed HET is very similar to that of a state-of-the-art xenon-fed thruster. Just as importantly, the current-voltage discharge characteristics of low power iodine-fed and xenon-fed thrusters are remarkably similar, potentially reducing development and qualifications costs by making it possible to use an already-qualified xenon-HET PPU in an iodine-fed system. Finally, a cold surface can be installed in a vacuum test chamber on which expended iodine propellant can deposit. In addition, the temperature doesn't have to be extremely cold to maintain a low vapor pressure in the vacuum chamber (it is under 10(exp -6) torr at -75 C), making it possible to 'cryopump' the propellant with lower-cost recirculating refrigerant-based systems as opposed to using liquid nitrogen or low temperature gaseous helium cryopanels. In the present paper, we describe testing performed using an iodine-fed 200 W Hall thruster mounted to a thrust stand and operated in conjunction with MSFCs Small Projects Rapid Integration and Test Environment (SPRITE) Portable Hardware In the Loop (PHIL) hardware. This work is performed in support of the iodine satellite (iSAT) project, which aims to fly a 200-W iodine-fed thruster on a 12-U CubeSat. The SPRITE PHIL hardware allows a given vehicle to do a checkout of its avionics algorithm by allowing it to monitor and feed data to simulated sensors and effectors in a digital environment. These data are then used to determine the attitude of the vehicle and a separate computer is used to interpret the data set and visualize it using a 3D graphical interface. The PHIL hardware allows the testing of the vehicles bus by providing 'real' hardware interfaces (in the case of this test a real RS422 bus) and specific components can be modeled to show their interactions with the avionics algorithm (e.g. a thruster model). For the iSAT project the PHIL is used to visualize the operating cycle of the thruster and the subsequent effect this thrusting has on the attitude of the satellite over a given period of time. The test is controlled using software running on an Andrews Space Cortex 160 flight computer. This computer is the current baseline for a full iSAT mission. While the test could be conducted with a lab computer and software, the team chose to exercise the propulsion system with a representative CubeSat-class computer. For purposes of this test, the "flight" software monitored the propulsion and PPU systems, controlled operation of the thruster, and provided thruster state data to the PHIL simulation. Commands to operate the thruster were initiated from an operator's workstation outside the vacuum chamber and passed through the Cortex 160 to exercise portions of the flight avionics. Two custom-designed pieces of electronics hardware have been designed to operate the propellant feed system. One piece of hardware is an auxiliary board that controls a latch valve, proportional flow control valves (PFCVs) and valve heaters as well as measuring pressures, temperatures and PFCV feedback voltage. An onboard FPGA provides a serial link for issuing commands and manages all lower level input-output functions. The other piece of hardware is a power distribution board, which accepts a standard bus voltage input and converts this voltage into all the different current-voltage types required to operate the auxiliary board. These electronics boards are located in the vacuum chamber near the thruster, exposing this hardware to both the vacuum and plasma environments they would encounter during a mission, with these components communicating to the flight computer through an RS-422 interface. The auxiliary board FPGA provides a 28V MOSFET switch circuit with a 20ms pulse to open or close the iodine propellant feed system latch valve. The FPGA provides a pulse width modulation (PWM) signal to a DC/DC boost converter to produce the 12-120V needed for control of the proportional flow control valve. There are eight MOSFET-switched heating circuits in the system. Heaters are 28V and located in the latch valve, PFCV, propellant tank and propellant feed lines. Both the latch valve and PFCV have thermistors built into them for temperature monitoring. There are also seven resistance temperature device (RTD) circuits on the auxiliary board that can be used to measure the propellant tank and feedline temperatures. The signals are conditioned and sent to an analog to digital converter (ADC), which is directly commanded and controlled by the FPGA.

Polzin, Kurt A.↗

Analysis of AC-DC Converters for Grid-tied High Temperature Steam Electrolysis Systems

Grid-tied HTSE systems have the prospects to produce clean hydrogen enabling power and broad energy systems decarbonization. Most commercially available power electronic converter systems (PECS) are designed for batteries, solar PVs, wind, and other well-established renewable energy resources. Standards (such as IEEE 1547, UL 1741, CA Rule-21, HI Rule14) exist for PECS used for renewable energy systems such as battery storage and solar PVs. However, those that consider the dynamic behavior of HTSEs and that can be used for large-scale H2 systems are yet to be developed. This paper investigates the performance of these PECS for the HTSE application that are set up at the Idaho National Laboratory for hydrogen production testing, research and development. In particular, the performance analysis of two grid-tied PECS (A and B) is conducted for a 100 kW solid oxide HTSE system. System A consists of 6 units of 30kW MOSFET-switched bidirectional AC-DC rectifier while system B has a single unit of 150kW thyristor-switched AC-DC rectifier. Both systems are connected to the HTSE stacks via a DC-DC converter. Different operational conditions of the HTSE system are tested to analyze the dynamic response of the HTSE’s PECS. The experimental results show the need to develop advanced control strategies for PECS that incorporates the dynamics of HTSE systems for improved performance.

High temperature steam electrolysis↗

Organic Direct-Bonded-Copper-Based Rapid Prototyping for Silicon Carbide Power Module Packaging

Silicon carbide (SiC) power devices are playing ever- growing roles in high-power-density power electronics converters by offering benefits such as high voltage rating, fast transients, and high thermal performance. Organic direct-bonded copper (ODBC)-based packaging, due to its ductility and ease of han- dling, allows the possibility of a more flexible layout design that may better tap the potential of SiC benefits. In this work, an ODBC-based prototyping routine is developed that accelerates the iterations of packaging layout design with low cost. The properties of ODBC and its handling are briefly introduced, and tools and fabrication steps are explained. Following this routine, a 1.2-kV SiC half-bridge power module is designed and fabricated with the focus on sub-nanohenry ultra-low loop inductance. Simulation and experimental validation are also conducted.

25 ENERGY STORAGE↗

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Zheng, Xinyu↗

7.2 kV Three-Port SiC Single-Stage Current-Source Solid-State Transformer With 90 kV Lightning Protection

This article proposes a multiport modular single-stage current-source solid-state transformer (SST) for applications like photovoltaic, energy storage integration, electric vehicle fast charging, data center, etc. The 7.2 kV 50 kVA current-source SST consists of five input-series output-parallel modules, each based on 3.3 kV SiC reverse-blocking MOSFET-plus-diode modules. The proposed SST has some unique features. First, compared to the voltage-source or matrix converter-based SSTs, the current-source SST has a unique advantage of single-stage isolated AC/DC or AC/AC conversion with an inductive DC link, but no medium-voltage (MV) AC experiments have been reported. This article for the first time demonstrates MV AC current-source SST up to 7.5 kV peak. Second, the multiport SST has a buffer port for active power decoupling (APD) or energy storage integration. The double-line-frequency power ripple from single-phase AC grid normally results in a large capacitor size in MV SSTs. The APD scheme is proposed in MV applications for the first time to enable a reduced DC link and the electrolytic capacitor-less SST with high reliability. Third, as a direct grid-connected converter without line-frequency transformer, insulation and protection are critical. A medium-frequency transformer design passes 55 kV basic-insulation level (BIL) and 60 kV high potential dielectrics withstand test with only 0.09% leakage inductance. Importantly, a lightning protection scheme is presented to protect the SST itself from 90 kV BIL impulse. Fourth, the proposed current-source SST topology is a modular soft-switching solid-state transformer (M-S4T) with full-range zero-voltage switching and controlled dv/dt for low electromagnetic interference. Furthermore, these concepts are verified in a three-port M-S4T prototype with forced oil cooling under single-module, stacked-module, steady-state, and dynamic operations.

14 SOLAR ENERGY↗

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Patterson, Richard↗

Quench protection for high-temperature superconductor cables using active control of current distribution

Superconducting magnets of future fusion reactors are expected to rely on composite high-temperature superconductor (HTS) cable conductors. In presently used HTS cables, current sharing between components is limited due to poorly defined contact resistances between superconducting tapes or by design. The interplay between contact and termination resistances is the defining factor for power dissipation in these cables and ultimately defines their safe operational margins. However, the current distribution between components along the composite conductor and inside its terminations is a priori unknown, and presently, no means are available to actively tune current flow distribution in real-time to improve margins of quench protection. Also, the lack of ability to electrically probe individual components makes it impossible to identify conductor damage locations within the cable. In this work, we address both problems by introducing active current control of current distribution between components using cryogenically operated metal-oxide-semiconductor-field-effect transistors (MOSFETs). We demonstrate through simulation and experiments how real-time current controls can help to drastically reduce heat dissipation in a developing hot spot in a two-conductor model system and help identify critical current degradation of individual cable components. Finally, prospects of other potential uses of MOSFET devices for improved voltage detection, AC loss-driven active quench protection, and remnant magnetization reduction in HTS magnets are also discussed.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Evaluation of GaAs FETs for cryogenic readout

Low-frequency, low-noise, low-power cryogenic electronics to read out photodetectors is being investigated for the star-tracking telescope of the Gravity Probe B spacecraft. We report our initial findings from evaluating more than 20 types of GaAs FETs, both commercial and non-commercial, for this application. Most exhibit useable dc characteristics at cryogenic temperatures, although gate leakage and hysteretic effects (presumably due to charge trapping) could be troublesome. Low-frequency noise (based primarily on grounded-gate measurements) at 4 K is '1/f-like' and for the quietest GaAs FETs appears to be at least as low as the lowest noise values reported for Si MOSFETs at 4 K. Further investigation is needed in several areas.

Kirschman, Randall K.↗

The BREKTRIA 500 – A Breakthrough in Technology and Power Density for an Advanced 500kW Utility-Scale String Inverter (Final Technical Report)

The primary goal of this development project, planned to be 36 months in duration, was to create a 500kW utility-scale string inverter, demonstrating an advanced hybrid architecture that would achieve unprecedented high power density, and bring the inverter to the stage of production readiness. Specific key objectives for the 500kW utility-scale string inverter were: Create a 500kW 3-phase 600Vac inverter that was similar in overall size to the existing 250kW string inverters in the market, thereby demonstrating dramatically increased power density; Achieve a cost of goods, including all manufacturing-related costs and overheads, at or below 2.5¢/Wac ($12,500); Demonstrate full-power operation at a 45-50C ambient temperature with no power de-rating; Accommodate a PV array DC input of up to 1MWdc, aka a DC/AC Ratio of 2.0; Demonstrate peak efficiency greater than 99% at any operating dc voltage, and a CEC weighted average efficiency greater than or equal to 98.5%. The motivation for this project was to leapfrog the competition by creating the world’s most powerful string inverter, utilizing an innovative topology and achieving a step change increase in power density. Achieving the goals of the project would have enabled Yaskawa Solectria Solar to demonstrate its technology leadership, manufacture the utility-scale string inverter in the company’s facilities in Illinois, and bring to the market a highly-differentiated and compelling product to help the company grow its share in the large and growing utility market segment. During the course of this project, BREK Electronics’ hybrid architecture inverter was taken from an early-stage 125kW prototype, to a more mature and successfully demonstrated power stage at twice the power. Two 250kW power stages were planned to build the 500kW inverter. Significant progress was made in the inverter controls, achieving a clean AC sinewave and closed-loop operation into the grid, and improved efficiency by control of the high-speed switching. Further, the updated 250kW power stage was on track to achieve full power operation at an ambient temperature of 50C. At the time of the project’s closure in September 2022, global semiconductor supply remained limited, with shortages creating dramatic swings in both availability and price. Given this situation, our ability to predict cost-of-goods two years out with any accuracy or confidence was limited. As a result, the probability of attaining the target cost of 2.5¢/Wac for the 500kW inverter remained uncertain at the closure of the project. This project successfully demonstrated the potential for the advanced hybrid architecture inverter that emerged from a decade of university research on Si IGBTs and SiC mosfets, leading to this unique inverter topology. The team has taken the first steps toward an evolutionary advancement in inverter technology that remains to be fully realized.

14 SOLAR ENERGY↗

Origin of Soft-Switching Output Capacitance Loss in Cascode GaN HEMTs at High Frequencies

Output capacitance (C OSS ) loss (E DISS ) is produced when the C OSS of a power device is charged and discharged, which ideally should be a lossless process. This loss was recently revealed to be a crucial concern for GaN high electron mobility transistors (HEMTs) in high-frequency soft-switching applications. Among various GaN devices, the composite-type, cascode GaN HEMT was reported to show the largest E DISS with a voltage dependence distinct from discrete GaN HEMTs. However, the physical origins of the EDISS in cascode GaN HEMTs remain unclear. This work fills this gap by identifying three loss components and, for the first time, experimentally quantifying them in the multi-MHz resonant switching. These loss components include a) the avalanche loss of Si MOSFET, b) the intrinsic E DISS of GaN HEMT, and c) the Si avalanche-induced GaN turn-ON loss. The last component was found to dominate E DISS at high voltage. By eliminating the Si avalanche and the associated loss components (a) and (c), the E DISS of cascode GaN HEMTs can be reduced by up to 75% at the price of an increase in output charge and switching transition time. Furthermore, these results provide new physical insights and practical guidelines to trim the soft-switching loss of cascode GaN HEMTs in high-frequency applications.

42 ENGINEERING↗

Analysis of AC-DC Converters for Grid-tied High Temperature Steam Electrolysis Systems

Grid-tied HTSE systems have the prospects to produce clean hydrogen enabling power and broad energy systems decarbonization. Most commercially available power electronic converter systems (PECS) are designed for batteries, solar PVs, wind, and other well-established renewable energy resources. Standards (such as IEEE 1547, UL 1741, CA Rule-21, HI Rule-14) exist for PECS used for renewable energy systems such as battery storage and solar PVs. However, those that consider the dynamic behavior of HTSEs and that can be used for large-scale H2 systems are yet to be developed. This paper investigates the performance of these PECS for the HTSE application that are set up at the Idaho National Laboratory for hydrogen production testing, research and development. In particular, the performance analysis of two grid-tied PECS (A and B) is conducted for a 100 kW solid oxide HTSE system. System A consists of 6 units of 30kW MOSFET-switched bidirectional AC-DC rectifier while system B has a single unit of 150kW thyristor-switched ACDC rectifier. Both systems are connected to the HTSE stacks via a DC-DC converter. Different operational conditions of the HTSE system are tested to analyze the dynamic response of the HTSE’s PECS. The experimental results show the need to develop advanced control strategies for PECS that incorporates the dynamics of HTSE systems for improved performance.

08 - HYDROGEN↗

Methodology of Low Inductance Busbar Design for Three-Level Converters

Three-level (3L) converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. In this article, the methodology of busbar layout design for 3L converters based on the magnetic cancellation effect is presented. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high-power 3L-active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and dc-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. Furthermore, the results match with each other, and the inductances of short and long loops are 6.5 and 17.5 nH, respectively, which are significantly lower than the busbars of NPC-type converters in other references.

42 ENGINEERING↗

Investigation of superlattice device structures

This report describes the investigation of growth properties, and the structure of epitaxial multilayer Si(Si(1x)Ge(x)) films grown on bulk Silicon Substrates. It also describes the fabrication and characterization of MOSFET and MESFET devices made on these epitaxial films. Films were grown in a CVD reactor using hydrides of Si and Ge with H2 and He as carrier gases. Growth temperatures were between 900 C and 1050 C with most films grown at 1000 C. Layer thickness was between 300A and 2000A and total film thickness was between 0.25 micro m and 7 micro m. The Ge content (X) in the alloy layers was between .05 and 0.2. N-type multilayer films grown on (100) p-type Si showed Hall mobility in the range 1000 to 1500 sq cm/v for an average carrier concentration of approx. 10 to the 16th power/cu cm. This is up to 50% higher than the Hall mobility observed in epitaxial Si films grown under the same conditions and with the same average carrier concentration. The mobility enhancement occurred in films with average carrier concentration (n) from 0.7 x 10 to the 16th power to 2 x 10 to the 17th power/cu cm, and total film thickness greater than 1.0 micro m. No mobility enhancement was seen in n-type multilayer films grown on (111) Si or in p-type multilayer films. The structure of the films was investigated was using SEM, TEM, AES, SIMS, and X-ray double crystal diffraction techniques. The film composition profile (AES, SIMS) showed that the transition region between layers is of the order of about 100A. The TEM examination revealed a well defined layered structure with fairly sharp interfaces and good crystalline quality. It also showed that the first few layers of the film (closest to the substrate) are uneven, most probably due to the initial growth pattern of the epitaxial film where growth occurs first in isolated islands that eventually growth and coalesce. The X-ray diffraction measurement determined the elastic strain and strain relief in the alloy layers of the film and the elastic strain in the intervening Si layers.

Gergis, I. S.↗

Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space

This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.

Krasowski, Michael J.↗