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Synchronization times reduced to reduce loss of data. Scheme for decoding received doubly encoded binary-data signal provides for joint synchronization of two decoders. Applies to concatenated error-correcting channel coding communication system in which, at transmitter, data first encoded by interleaved Reed-Solomon code (block code), then by convolutional code.
This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.
Solving the hard Satisfiability Problem is time consuming even for modest-sized problem instances. Solving the Random L-SAT Problem is especially difficult due to the ratio of clauses to variables. This report presents a parallel synchronous simulated annealing method for solving the Random L-SAT Problem on a large-scale distributed-memory multiprocessor. In particular, we use a parallel synchronous simulated annealing procedure, called Generalized Speculative Computation, which guarantees the same decision sequence as sequential simulated annealing. To demonstrate the performance of the parallel method, we have selected problem instances varying in size from 100-variables/425-clauses to 5000-variables/21,250-clauses. Experimental results on the AP1000 multiprocessor indicate that our approach can satisfy 99.9 percent of the clauses while giving almost a 70-fold speedup on 500 processors.
A constant outward radial thrust acceleration can be used to reduce the radius of a circular orbit of specified period. Heliocentric circular orbits are designed to match the orbital period of Earth or Mars for various radial thrust accelerations and are defined as synchronous orbits. Minimum-time solar sail orbit transfers to these synchronous heliocentric orbits are presented.
Gear cracks are typically difficult to diagnose with sufficient time before catastrophic damage occurs. Significant damage must be present before algorithms appear to be able to detect the damage. Frequently there are multiple gear meshes on a single shaft. Since they are all synchronous with the shaft frequency, the commonly used synchronous averaging technique is ineffective in removing other gear mesh effects. Carefully applying a filter to these extraneous gear mesh frequencies can reduce the overall vibration signal and increase the accuracy of commonly used vibration metrics. The vibration signals from three seeded fault tests were analyzed using this filtering procedure. Both the filtered and unfiltered vibration signals were then analyzed using commonly used fault detection metrics and compared. The tests were conducted on aerospace quality spur gears in a test rig. The tests were conducted at speeds ranging from 2500 to 5000 revolutions per minute and torques from 184 to 228 percent of design load. The inability to detect these cracks with high confidence results from the high loading which is causing fast fracture as opposed to stable crack growth. The results indicate that these techniques do not currently produce an indication of damage that significantly exceeds experimental scatter.
The research reports on the development of a whole-field, system-level interferometry technique having phase-synchronized data acquisition and adjustable phase triggering. The technique utilizes a Fizeau interferometer, arbitrary function generator, oscilloscope, trigger filter, and CCD camera to determine the out-of-plane modal frequencies of a thin, highly reflective membrane. The technique generates phase-adjustable CCD camera trigger signals that are synchronized to the audio frequency excitation signal. The surface figures from the resulting interferograms were evaluated with fringe-following software and compared against that of an ideal membrane vibrating at resonance.
In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.
The purpose of this paper is to describe a new method for thermal nondestructive evaluation. This method uses a synchronized electronic shutter system (SESS) to remove the heat lamp's influence on the thermal data during and after flash heating. There are two main concerns when using flash heating. The first concern is during the flash when the photons are reflected back into the camera. This tends to saturate the detectors and potentially introduces unknown and uncorrectable errors when curve fitting the data to a model. To address this, an electronically controlled shutter was placed over the infrared camera lens. Before firing the flash lamps, the shutter is opened to acquire the necessary background data for offset calibration. During flash heating, the shutter is closed to prevent the photons from the high intensity flash from saturating the camera's detectors. The second concern is after the flash heating where the lamps radiate heat after firing. This residual cooling introduces an unwanted transient thermal response into the data. To remove this residual effect, a shutter was placed over the flash lamps to block the infrared heat radiating from the flash head after heating. This helped to remove the transient contribution of the flash. The flash lamp shutters were synchronized electronically with the camera shutter. Results are given comparing the use of the thermal inspection with and without the shutter system.
Endogenous circadian clocks are robust regulators of physiology and behavior. Synchronization or entrainment of biological clocks to environmental time is adaptive and important for physiological homeostasis and for the proper timing of species-specific behaviors. We studied subjects in the laboratory for up to 55 days each to determine the ability to entrain the human clock to a weak circadian synchronizing stimulus [scheduled activity-rest cycle in very dim (approximately 1.5 lux in the angle of gaze) light-dark cycle] at three approximately 24-h periods: 23.5, 24.0, and 24.6 h. These studies allowed us to test two competing hypotheses as to whether the period of the human circadian pacemaker is near to or much longer than 24 h. We report here that imposition of a sleep-wake schedule with exposure to the equivalent of candle light during wakefulness and darkness during sleep is usually sufficient to maintain circadian entrainment to the 24-h day but not to a 23.5- or 24.6-h day. Our results demonstrate functionally that, in normally entrained sighted adults, the average intrinsic circadian period of the human biological clock is very close to 24 h. Either exposure to very dim light and/or the scheduled sleep-wake cycle itself can entrain this near-24-h intrinsic period of the human circadian pacemaker to the 24-h day.
In this report, we examined if the synchronization of muscle sympathetic nerve activity (MSNA) with muscle contraction is enhanced by limb congestion. To explore this relationship, we applied signal-averaging techniques to the MSNA signal obtained during short bouts of forearm contraction (2-s contraction/3-s rest cycle) at 40% maximal voluntary contraction for 5 min. We performed this analysis before and after forearm venous congestion; an intervention that augments the autonomic response to sustained static muscle contractions via a local effect on muscle afferents. There was an increased percentage of the MSNA noted during second 2 of the 5-s contraction/rest cycles. The percentage of total MSNA seen during this particular second increased from minute 1 to 5 of contraction and was increased further by limb congestion (control minute 1 = 25.6 +/- 2.0%, minute 5 = 32.8 +/- 2.2%; limb congestion minute 1 = 29.3 +/- 2.1%, minute 5 = 37.8 +/- 3.9%; exercise main effect <0.005; limb congestion main effect P = 0.054). These changes in the distribution of signal-averaged MSNA were seen despite the fact that the mean number of sympathetic discharges did not increase over baseline. We conclude that synchronization of contraction and MSNA is seen during short repetitive bouts of handgrip. The sensitizing effect of contraction time and limb congestion are apparently due to feedback from muscle afferents within the exercising muscle.
Various disturbances that are synchronous with the shaft speed can complicate radial magnetic bearing control. These include position sensor target irregularities (runout) and shaft imbalance. The method presented here allows the controller to ignore all synchronous harmonics of the shaft position input (within the closed-loop bandwidth) and to respond only to asynchronous motions. The result is reduced control effort.
The development of an advanced robust timing synchronization scheme is crucial for the support of two NASA programs--Advanced Air Transportation Technologies and Aviation Safety. A mobile aeronautical channel is a dynamic channel where various adverse effects--such as Doppler shift, multipath fading, and shadowing due to precipitation, landscape, foliage, and buildings--cause the loss of symbol timing synchronization.
Embedded distributed systems have become an integral part of many safety-critical applications. There have been many attempts to solve the self-stabilization problem of clocks across a distributed system. An analysis of one such protocol called the Byzantine Self-Stabilizing Pulse Synchronization (BSS-Pulse-Synch) protocol from a paper entitled "Linear Time Byzantine Self-Stabilizing Clock Synchronization" by Daliot, et al., is presented in this report. This report also includes a discussion of the complexity and pitfalls of designing self-stabilizing protocols and provides counter-examples for the claims of the above protocol.
In a previous publication [1], an iterative closed-loop carrier synchronization scheme for binary phase-shift keyed (BPSK) modulation was proposed that was based on feeding back data decisions to the input of the loop, the purpose being to remove the modulation prior to carrier synchronization as opposed to the more conventional decision-feedback schemes that incorporate such feedback inside the loop. The idea there was that, with sufficient independence between the received data and the decisions on it that are fed back (as would occur in an error-correction coding environment with sufficient decoding delay), a pure tone in the presence of noise would ultimately be produced (after sufficient iteration and low enough error probability) and thus could be tracked without any squaring loss. This article demonstrates that, with some modification, the same idea of iterative information reduction through decision feedback can be applied to quadrature phase-shift keyed (QPSK) modulation, something that was mentioned in the previous publication but never pursued.
This paper presents a methodology of detecting rotor imbalances, such as mass imbalance and crack-induced imbalance, using shaft synchronous vibrations. An iterative scheme is developed to identify parameters from measured synchronous vibration data. A detection system is integrated by using state-of-the-art commercial analysis equipment. A laboratory rotor test rig is used to verify the system integration and algorithm validation. A real engine test has been carried out and the results are reported.
A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.
An apparatus for and a method of triggering a pulsed light source, in particular a laser light source, for predictable capture of the source by video equipment. A frame synchronization signal is derived from the video signal of a camera to trigger the laser and position the resulting laser light pulse in the appropriate field of the video frame and during the opening of the electronic shutter, if such shutter is included in the camera. Positioning of the laser pulse in the proper video field allows, after recording, for the viewing of the laser light image with a video monitor using the pause mode on a standard cassette-type VCR. This invention also allows for fine positioning of the laser pulse to fall within the electronic shutter opening. For cameras with externally controllable electronic shutters, the invention provides for background light suppression by increasing shutter speed during the frame in which the laser light image is captured. This results in the laser light appearing in one frame in which the background scene is suppressed with the laser light being uneffected, while in all other frames, the shutter speed is slower, allowing for the normal recording of the background scene. This invention also allows for arbitrary (manual or external) triggering of the laser with full video synchronization and background light suppression.
A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.