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Digital portion of power supply synchronizer used in forming subsystem on single silicon slice - logic design, interconnect pattern, nonlinear load switch and packaging
The theory and experimental verification of a method of detecting fluid-mass loss, expansion-chamber pressure loss, or excessive vapor build-up in NASA's Airborne Information Management System (AIMS) are presented. The primary purpose of this leak-detection method is to detect the fluid-mass loss before the volume of vapor on the liquid side causes a temperature-critical part to be out of the liquid. The method detects the initial leak after the first 2.5 pct of the liquid mass has been lost, and it can be used for detecting subsequent situations including the leaking of air into the liquid chamber and the subsequent vapor build-up.
Key elements of space qualification of opto-electric and photonic optical devices were overviewed. Efforts were concentrated on the reliability concerns of the devices needed for potential applications in space environments. The ultimate goal for this effort is to gradually establish enough data to develop a space qualification plan of newly developed specific photonic parts using empirical and numerical models to assess the life-time and degradation of the devices for potential long term space missions.
A wake shield space processing facility (10) for maintaining ultra-high levels of vacuum is described. The wake shield (12) is a truncated hemispherical section having a convex side (14) and a concave side (24). Material samples (68) to be processed are located on the convex side of the shield, which faces in the wake direction in operation in orbit. Necessary processing fixtures (20) and (22) are also located on the convex side. Support equipment including power supplies (40, 42), CMG package (46) and electronic control package (44) are located on the convex side (24) of the shield facing the ram direction. Prior to operation in orbit the wake shield is oriented in reverse with the convex side facing the ram direction to provide cleaning by exposure to ambient atomic oxygen. The shield is then baked-out by being pointed directed at the sun to obtain heating for a suitable period.
Commercial silicon carbide and silicon Schottky barrier power diodes have been subjected to 203 MeV proton irradiation and the effects of the resultant displacement damage on the I-V characteristics have been observed. Changes in forward bias I-V characteristics are reported for fluences up to 4 x 10(exp 14) p/cm2. For devices of both material types, the series resistance is observed to increase as the fluence increases. The changes in series resistance result from changes in the free carrier concentration due to carrier removal by the defects produced. A simple model is presented that allows calculation of the series resistance of the device and then relates the carrier removal rate to the changes in series resistance. Using this model to calculate the carrier removal rate in both materials reveals that the carrier removal rate in silicon is less than that in silicon carbide, indicating that silicon is the more radiation tolerant material.
The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs.
Radiation requirements and trends. TID: 1) >90% of NASA applications are < 100 krads-Si in piecepart requirements. a) Many commercial devices (NVM and SDRAMs) meet or come close to this. b) Charge pump TID tolerance has improved an order magnitude over the last 10 years. 2) There are always a few programs with higher level needs and, of course, defense needs SEL: 1) Prefer none or rates that are considered low risk. a) Latent damage is a bear to deal with. 2) As we re packing cells tighter and even with lower Vdd, we re seeing SEL on commercial devices regularly (<90nm). a) Often in power conversion, I/O, or control areas. SEU: 1) It s not the bit errors, it s the SEFIs errors that are the biggest issues. a) Scrubbing concerns for risk, power, speed.
The Diamond AVIM optical fiber connector has been used for over a decade in flight environments. AVIM which stands for Aviation Intermediate Maintenance is always referenced as a fiber optic connector type from the DIN (Deutsches Institut fur Normung) family of optical fiber connectors. The newly available Mini AVIM and DMI (Definition Multimedia Interface) connectors also by Diamond provide similar features as the high performance AVIM with the added benefits of being small form factor for board mount and internal box use where long connectors and strain relief can not be accommodated. Transceiver, fiber laser technology and receiver optic technology based on small sized constraints will benefit the most by the reduction in connector form factor. It is for this reason that the Mini AVIM is being evaluated for multimode and single mode optical fiber use in both fiber based and cable based packaging configurations. In a fiber based termination, there are no cable materials to bond to the connector. The only bonding that is conducted is the mounting of the fiber with epoxy to the connector ferrules (which are called DMI ferrules). In a cable configuration, the compatibility of the connector subcomponents along with the upjacketing materials of the cable around the fiber needs to be considered carefully for termination fabrication. Cabled terminations will show greater insertion loss and high probability of failures during thermal cycling testing. This is due to the stressing of the combination of materials that each have different Coefficients of Thermal Expansion (CTE's) and that are bonded together to the connector subcomponents. As the materials flex during thermal excursions, forces are applied to the termination and can make the system fail if the grouping of materials (per their CTE's) are not compatible and this includes cable materials, epoxies, ferrule and connector body components. For this evaluation, multimode 100 micron core step index fiber was used for the fiber terminated condition, and single mode SMF-28 upjacketed with W.L. Gore Flexlite was used for the cabled configuration. For background purposes, a comparison is presented here for information purposes between the high performance AVIM connector features and the Mini AVIM small form factor connectors. Basic connector features are described here.
Presentation discusses: (1) Why Multi-Layer Ceramic Capacitors(MLCCs) crack during manual soldering? Workmanship and parts issues. (2) Do existing qualification requirements assure crack-free soldering? MIL-spec Thermal Shock (TS) testing. MIL-spec Resistance to Soldering Heat (RSH) test. (3) What test can assure reliable soldering? Mechanical characteristics of ceramics. Comparison of three TS techniques: LND, TSD, and IWT. (4) Simulation of TS conditions.
Single-event-effect test results for hi-rel total-dose-hardened power MOSFETs are presented in this report. TheSCF9550 from Semicoa and the IRHM57260SE from International Rectifier were tested to NASA test condition/standards and requirements.The IRHM57260SE performed much better when compared to previous testing. These initial results confirm that parts from the Temecula line are marginally comparable to the El Segundo line. The SCF9550 from Semicoa was also tested and represents the initial parts offering from this vendor. Both parts experienced single-event gate rupture (SEGR) and single-event burnout (SEB). All of the SEGR was from gate to drain.
Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.
The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).
No abstract available
Highly Accelerated Life Testing (HALT) testing holds promise for affordable efficient acceptance testing of multi-layer ceramic chip capacitors (MLCCs) especially for commercial off the shelf (COTS).
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.
The presentation provides an updated, high-level overview of the NEPP Program. The latest organizational chart is presented that shows the names of the Program and Assistant Program Managers. Additionally, the recent work that is on-going with the updating of several NASA NPDs, NPRs and technical standards is reviewed. Internal and external organizational interfaces are described. Finally, the current technology focus areas are described. These areas include passives, wide-band gap power devices, processor units (CPUs and GPUs), 2.5D and 3D device architectures, memories, and data analytics.