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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17

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NASA NTRS2000

Characteristics of Monolithically Integrated InGaAs Active Pixel Imager Array

Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.

Kim, Q.↗

NASA NTRS2016

Open Source Radiation Hardened by Design Technology

The proposed technology allows use of the latest microcircuit technology with lowest power and fastest speed, with minimal delay and engineering costs, through new Radiation Hardened by Design (RHBD) techniques that do not require extensive process characterization, technique evaluation and re-design at each Moore's Law generation. The separation of critical node groups is explicitly parameterized so it can be increased as microcircuit technologies shrink. The technology will be open access to radiation tolerant circuit vendors. INNOVATION: This technology would enhance computation intensive applications such as autonomy, robotics, advanced sensor and tracking processes, as well as low power applications such as wireless sensor networks. OUTCOME / RESULTS: 1) Simulation analysis indicates feasibility. 2)Compact voting latch 65 nanometer test chip designed and submitted for fabrication -7/2016. INFUSION FOR SPACE / EARTH: This technology may be used in any digital integrated circuit in which a high level of resistance to Single Event Upsets is desired, and has the greatest benefit outside low earth orbit where cosmic rays are numerous.

Shuler, Robert↗

NASA NTRS1994

Integration and test of high-speed transmitter electronics for free-space laser communications

The NASA Lewis Research Center in Cleveland, Ohio, has developed the electronics for a free-space, direct-detection laser communications system demonstration. Under the High-Speed Laser Integrated Terminal Electronics (Hi-LITE) Project, NASA Lewis has built a prototype full-duplex, dual-channel electronics transmitter and receiver operating at 325 megabit S per second (Mbps) per channel and using quaternary pulse-position modulation (QPPM). This paper describes the integration and testing of the transmitter portion for future application in free-space, direct-detection laser communications. A companion paper reviews the receiver portion of the prototype electronics. Minor modifications to the transmitter were made since the initial report on the entire system, and this paper addresses them. The digital electronics are implemented in gallium arsenide integrated circuits mounted on prototype boards. The fabrication and implementation issues related to these high-speed devices are discussed. The transmitter's test results are documented, and its functionality is verified by exercising all modes of operation. Various testing issues pertaining to high-speed circuits are addressed. A description of the transmitter electronics packaging concludes the paper.

Soni, Nitin J.↗

NASA NTRS2019

Vorago RH-OBC-1 Single Event Effect Characterization Test Report

The Vorago Technologies RH-OBC-1 is a CubeSat Kit Bus compatible single board computer with a Vorago VA10820 ARM Cortex-M0 microcontroller at its core. The board also includes a set of common peripheral integrated circuits, like voltage regulators, non-volatile memories (NVM), an analog-to-digital converter (ADC), a watchdog/supervisor, and a Controller Area Network (CAN) bus transceiver. High-energy proton (200 MeV) testing was conducted at both board and component levels to investigate single-event effects.

CubeSat compatible board↗

NASA NTRS2008

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

Samoska, Lorene↗

DOE OSTI2025

SpacelyProject/spacely-docs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions. Spacely was originally developed at Fermi National Accelerator Laboratory.

Quinn, Adam [Fermi National Accelerator Laboratory↗

NASA NTRS1973

Parts, materials, and processes experience summary, volume 2

This summary provides the general engineering community with the accumulated experience from ALERT reports issued by NASA and the Government-Industry. Data Exchange Program, and related experience gained by Government and industry. It provides expanded information on selected topics by relating the problem area (failure) to the cause, the investigation and findings, the suggestions for avoidance (inspections, screening tests, proper part applications, requirements for manufacturer's plant facilities, etc.), and failure analysis procedures. Diodes, integrated circuits, and transistors are covered in this volume.

Source record↗

NASA NTRS1981

Solar cell modules for plasma interaction evaluation

A plasma interaction analysis in support of the solar electric propulsion subsystem examined the effects of a large high voltage solar array interacting with an ion thruster produced plasma. Two solar array test modules consisting of 36 large area wraparound contact solar cells welded to a flexible Kapton integrated circuit substrate were abricated. The modules contained certain features of the effects of insulation, din-holes, and bonding of the cell to the substrate and a ground plane. The possibility of a significant power loss occurring due to the collection of charged particles on the solar array interconnects was the focus of the research.

Source record↗

NASA NTRS1983

Test Pattern for IC's

Random-fault densities measured in array of standard structures. Test pattern is array of standard circuit elements built into circuit chip along with, or in lieu of, integrated circuit objective process. Measurements on ray made and interpreted so fabrication process can be corrected as necessary.

Griswold, T. W.↗

NASA NTRS1985

Protective Cover for IC Packages

Aluminized plastic protects integrated circuits from static discharge. Snap-on cover shorts leads of integrated-circuit flatpack to prevent damage from electrostatic discharges during transport, installation, or other handling before final testing. Cover removed only during lead bending and testing.

Borden, T. J.↗

NASA NTRS1987

Measuring Conductor Widths and Spacings Electrically

Widths and spacings of conductor lines on integrated circuits measured electrically by split cross-bridge resistor technique. Speeds evaluation of integrated-circuit fabrication processes. When measurement of probe currents and voltages and reduction of measurement data automated, test structure probed and characterized in less than one second.

Buehler, Martin G.↗

NASA NTRS1986

RF characterization of monolithic microwave and mm-wave ICs

A number of fixturing techniques compatible with automatic network analysis are presented. The fixtures are capable of characterizing GaAs Monolithic Microwave Integrated Circuits (MMICs) at K and Ka band. Several different transitions are used to couple the RF test port to microstrip. Fixtures which provide chip level de-embedding are included. In addition, two advanced characterization techniques are assessed.

Romanofsky, R. R.↗

NASA NTRS1977

Storage effects on cells

The results of an experiment to test storage effects on electric cells of a battery are presented and discussed. The type of cells were the 20 amp-hour OAO type. The various modes that were tested were the integration type mode, the trickle charge, the discharge shorted and the discharged OCV (open current voltage). Every six months the cells were reconditioned and approximately two weeks of tests were performed. The tests included three capacity checks, two zero-degree overcharge tests and an internal short test (the cells are shunted for 16 hours, the shunt removed and allowed to stand on local circuit recovery for 24 hours). The integration pack was discontinued after three years and the trickle charge shorted packs after five years.

Harkness, J. M.↗

DOE OSTI2026

TTDAQ: A Continuous Flow, Timing and Trigger DAQ System

Final Scientific/Technical Report for DOE Award DE-SC0019581, “TTDAQ: A Continuous Flow, Timing and Trigger DAQ System.” The report summarizes Telluric Labs’ Phase II STTR work developing silicon-photonic building blocks for a software-defined, continuous-flow, trigger-less data acquisition system for next-generation high-energy and nuclear-physics detectors. The project focused on radiation-hard photonic integrated circuits, remote optical illumination, dense wavelength-division multiplexing, and a differential microring-resonator transceiver architecture designed to improve high-speed optical link stability and bandwidth. The report describes project objectives, technical accomplishments, AIM Photonics tape-outs, bench characterization, radiation-hardness testing, deferred integration work, and potential applications beyond physics readout.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS1988

Comb/serpentine/cross-bridge test structure for fabrication process evaluation

The comb/serpentine/cross-bridge structure was developed to monitor and evaluate same layer shorts and step coverage problems (open and high-resistance wire over steps) for integrated circuit fabrication processes. The cross-bridge provides local measurements of wire sheet resistance and wirewidth. These local parametric measurements are used in the analysis of the serpentine wire, which identifies step coverage problems. The comb/serpentine/cross-bridge structure was fabricated with 3 microns CMOS/bulk p-well process and tested using a computer-controlled parametric test system.

Sayah, Hoshyar R.↗

NASA NTRS2011

An Integrated 520-600 GHz Sub-Harmonic Mixer and Tripler Combination Based on GaAs MMIC Membrane Planar Schottky Diodes

We present here the design, development and test of an integrated sub-millimeter front-end featuring a 520-600 GHz sub-harmonic mixer and a 260-300 GHz frequency tripler in a single cavity. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional machined as well as silicon micro-machined blocks. Measurement results on the metal block give best DSB mixer noise temperature of 2360 K and conversion losses of 7.7 dB at 520 GHz. Preliminary results on the silicon micro-machined blocks give a DSB mixer noise temperature of 4860 K and conversion losses of 12.16 dB at 540 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer for both packages is between 30 and 50 mW

passively cooled detectors↗

NASA NTRS1976

High and low threshold P-channel metal oxide semiconductor process and description of microelectronics facility

The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs.

Bouldin, D. L.↗

NASA NTRS1977

Microprocessor Seminar, phase 2

Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.

Scott, W. R.↗