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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Long-term prediction test procedure for most ICs, based on linear response theory

Experimentally, thermal annealing is known to be a factor which enables a number of different integrated circuits (IC's) to recover their operating characteristics after suffering radiation damage in the space radiation environment; thus, decreasing and limiting long term cumulative total-dose effects. This annealing is also known to be accelerated at elevated temperatures both during and after irradiation. Linear response theory (LRT) was applied, and a linear response function (LRF) to predict the radiation/annealing response of sensitive parameters of IC's for long term (several months or years) exposure to the space radiation environment were constructed. Compressing the annealing process from several years in orbit to just a few hours or days in the laboratory is achieved by subjecting the IC to elevated temperatures or by increasing the typical spaceflight dose rate by several orders of magnitude for simultaneous radiation/annealing only. The accomplishments are as follows: (1) the test procedure to make predictions of the radiation response was developed; (2) the calculation of the shift in the threshold potential due to the charge distribution in the oxide was written; (3) electron tunneling processes from the bulk Si to the oxide region in an MOS IC were estimated; (4) in order to connect the experimental annealing data to the theoretical model, constants of the model of the basic annealing process were established; (5) experimental data obtained at elevated temperatures were analyzed; (6) time compression and reliability of predictions for the long term region were shown; (7) a method to compress test time and to make predictions of response for the nonlinear region was proposed; and (8) nonlinearity of the LRF with respect to log(t) was calculated theoretically from a model.

Litovchenko, V.↗
NASA NTRS1981

Automatic gain control

An automatic gain control (AGC), designed to operate with the prototype Loran-C receiver, is described. The device is used to eliminate error which occurs when signals are received at different magnitudes. The automatic gain control is a three transistor circuit which requires a constant dc voltage of 8 volts. Tests conclude that this value may be in the range of 4 to 12 v without change in circuit performance. Two transistors are cascaded to pass and amplify the input signal. Their gain is controlled by a third transistor which itself is controlled by an external AGC voltage between 0 and 8 volts dc. The integrated circuit used is an 8 pin chip, which is a differential cascade amplifier designed for use in communications operating at frequencies from dc to 120 MHz. The integrated circuit was balanced for AGC capabilities, and has a wide operating current range. The maximum input current at pins 1 and 5 is 0.1 mAmps. AGC testing is described.

Roman, J. P.↗
NASA NTRS1989

Common source cascode amplifiers for integrating IR-FPA applications

Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.

Woolaway, James T.↗
NASA NTRS1972

Mission oriented R and D and the advancement of technology: The impact of NASA contributions, volume 2

NASA contributions to the advancement of major developments in twelve selected fields of technology are presented. The twelve fields of technology discussed are: (1) cryogenics, (2) electrochemical energy conversion and storage, (3) high-temperature ceramics, (4) high-temperature metals (5) integrated circuits, (6) internal gas dynamics (7) materials machining and forming, (8) materials joining, (9) microwave systems, (10) nondestructive testing, (11) simulation, and (12) telemetry. These field were selected on the basis of both NASA and nonaerospace interest and activity.

Robbins, M. D.↗
NASA NTRS1987

Theory of Periodic-Binary-Sequence Generators

Algorithms yield feedback shift registers with maximum regularity. Report provides extensive mathematical treatment of new and previous results related to generation of pseudo-noise binary sequences by feedback shift registers. Generator architectures amenable to efficient implementation in very-large-scale integrated (VLSI) circuits. Report includes literature references to applications of such sequences in random-number generation, radar, VLSI testing, data encryption and decryption, algebraic error-detection and error-correction encoding and decoding, and feedback-shift-register synthesis of sequential machines.

Perlman, M.↗
NASA NTRS1991

Programmable Maintenance Processor For XAIDS

Programmable maintenance processor (MAINT) made of commercially available integrated circuits. Autonomous one of four digital electronic processors in extended aircraft interrogation and display system (XAIDS). Developed for testing of system and application computer programs as well as for testing equipment. MAINT has independent terminal and printer interfaces and dedicated magnetic bubble memory storing system-testing sequences entered from terminal. Software for MAINT written in PLM86 programming language and broken into four separate modules.

Glover, Richard↗
NASA NTRS1997

Radiation Effects on Current Field Programmable Technologies

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Katz, R.↗
NASA NTRS2018

Evaluation of Space Radiation Effects on HgCdTe Avalanche Photodiode Arrays for Lidar Applications

We report the results from proton and gamma ray radiation testing of HgCdTe avalanche photodiode (APD) arrays developed by Leonardo DRS for space lidar detectors. We tested these devices with both approximately 60 MeV protons and gamma rays, with and without the read out integrated circuit (ROIC). We also measured the transient responses with the device fully powered and with the APD gain from unity to greater than 1000. The detectors produced a large current impulse in response to each proton hit but the response completely recovered within 1 microsecond. The devices started to have persistent damage at a proton fluence of 7e10 protons/cm2, equivalent to 10 krad(Si) total ionization dose. The dark current became much higher after the device was warmed to room temperature and cooled to 80K again, but it completely annealed after baking at 85 C for several hours. These results showed the HgCdTe APD arrays are suitable for use in space lidar for typical Earth orbiting and planetary missions provided that provisions are made to heat the detector chip to 85 C for several hours after radiation damage becomes evident that system performance is impacted.

Sun, Xiaoli↗
NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗
NASA NTRS1992

Thermal verification testing of commercial printed-circuit boards for spaceflight

A method developed to verify commercial printed-circuit boards for a Shuttle orbital flight is discussed. The test sequence is based on early fault detection, desire to test the final assembly, and integration with other verification testing. A component thermal screening test is performed first to force flaws in design, workmanship, parts, processes, and materials into observable failures. Temperature definition and vibration tests are performed next. Final assembly testing is performed to simulate the Shuttle flight. An abbreviated thermal screening test is performed as a check after the vibration test, and then a complete thermal operational test is performed. The final assembly test finishes up with a burn-in of 100 h of trouble-free operation. Verification is successful when all components and final assemblies have passed each test. This method was very successful in verifying that commercial printed-circuit boards will survive in the Shuttle environment.

Foster, William M., II↗
NASA NTRS1992

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.

Fouts, Douglas J.↗
NASA NTRS2000

High-Speed Automated Tester for Vacuum Chamber Feedthrough Connectors and Cables

The Goddard Space Flight Center's thermal vacuum laboratory has developed a high-speed automated system for testing the integrity of 37-pin MIL-C-5015 cylindrical electrical feedthrough connectors used on penetration plates of thermal vacuum chambers. The system consists of a desktop PC driving a data acquisition front end. The latter measures the resistance through each pin of the connector and the resistance from each pin to all other pins and the connector shell. In addition to identifying unacceptable feedthroughs, the system is also used for testing cables. In the special case of Type T thermocouples (used almost exclusively at the lab), the difference in resistance between the copper and constantan wires provides positive proof of accidentally reversed connector wiring. Data acquisition time to completely test a cable or feedthrough connector is less than thirty seconds. The system provides a hardcopy printout of the resistance readings. Connectors or cables with fewer wires are tested using simple adapter cables. Initial tests indicate that the performance of a given feedthrough connector can be predicted on the basis of measured resistance readings, reducing ongoing cost of connector replacement. The opportunity to positively certify the integrity of cables, cable connectors and feedthroughs before the start of a thermal vacuum test minimizes the likelihood of a circuit problem that would require returning the chamber to ambient conditions for repair. This system has two principal advantages for the Goddard thermal vacuum laboratory. Its only significant cost was the labor to fabricate the test cable and shorting cable -- about 40 man-hours total. The system was built around a computer and data acquisition unit that were already on hand. The second advantage is that it very quickly tests both of the parameters that are essential.

Swope, Robert H.↗
NASA NTRS2007

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗
NASA NTRS2016

Field Programmable Gate Aray (FPGA) Radiation Data: All Data is Not Equal

Electronic parts (integrated circuits) have grown in complexity such that determining all failure modes and risks based on single particle event radiation testing is impossible. In this presentation, the authors will present why this is so and provide some realism on what this means to FPGAs. Its all about understanding actual risks and not making assumptions.

radiation testing↗
NASA NTRS1999

On-Wafer Testing of Circuits Through 220 GHz

We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

Gaier, Todd↗
NASA NTRS2018

Stirling Convertor Controller Development at NASA Glenn Research Center

For nearly two decades, NASA Glenn Research Center (GRC) has been supporting the development of Radioisotope Power Systems (RPS). NASA desires higher conversion efficiency RPS options that are reliable and robust with long life design. Dynamic conversion, such as Stirling and Brayton, offer the potential for higher conversion efficiencies than current RPS but have yet to be demonstrated in a flight application. The RPS program sent out a solicitation to investigate options for dynamic conversion technologies. As a result of this solicitation, four dynamic power convertor (DPC) technologies were selected for design and three are proceeding to the fabrication phase of prototype dynamic convertors. One lesson learned from the Advanced Stirling Radioisotope Generator (ASRG) project is that controller development should be coordinated with the development of a dynamic convertor. As a result of this, NASA GRC has been utilizing hardware from past Stirling convertor projects including that of the ASRG to support controller development for the DPC's. NASA GRC has developed a strong knowledge base on both analog and digital Stirling dynamic power convertor controllers and will continue to expand and apply that knowledge to the DPC's. Over the past 15 years, controllers were developed at GRC, at Lockheed Martin (LM) and by the Johns Hopkins University/Applied Physics Laboratory (JHU/APL). Various generations of the controllers have been developed as lessons were learned through various component and system level tests. Some of the tests performed were fault tolerance, flight acceptance vibration, electromagnetic interference (EMI), spacecraft integration, and extended operation. The fault tolerance test characterized the controller's ability to handle various fault conditions, including high or low bus power consumptions, total open load or short circuit, and replacing a failed controller card while the backup maintains control of the Stirling convertor. The vibration test confirms the controller's ability to control an ASC during launch. The EMI test characterized the AC and DC magnetic and electric fields emitted by the single ASC and if the controller has an impact on the radiated EMI. Spacecraft integration testing in the Radioisotope Power Systems System Integration Laboratory (RSIL) provided insight into the electrical interactions between the representative RPS, its associated control schemes, and realistic electric system loads. The extended operation test allows data to be collected over a period of thousands of hours to obtain long term performance data of the system. This paper describes the history of controller development at NASA GRC, tests performed on these controllers, and lessons learned.

Dugala, Gina M.↗
NASA NTRS2011

Cable Tester Box

Cables are very important electrical devices that carry power and signals across multiple instruments. Any fault in a cable can easily result in a catastrophic outcome. Therefore, verifying that all cables are built to spec is a very important part of Electrical Integration Procedures. Currently, there are two methods used in lab for verifying cable connectivity. (1) Using a Break-Out Box and an ohmmeter this method is time-consuming but effective for custom cables and (2) Commercial Automated Cable Tester Boxes this method is fast, but to test custom cables often requires pre-programmed configuration files, and cables used on spacecraft are often uniquely designed for specific purposes. The idea is to develop a semi-automatic continuity tester that reduces human effort in cable testing, speeds up the electrical integration process, and ensures system safety. The JPL-Cable Tester Box is developed to check every single possible electrical connection in a cable in parallel. This system indicates connectivity through LED (light emitting diode) circuits. Users can choose to test any pin/shell (test node) with a single push of a button, and any other nodes that are shorted to the test node, even if they are in the same connector, will light up with the test node. The JPL-Cable Tester Boxes offers the following advantages: 1. Easy to use: The architecture is simple enough that it only takes 5 minutes for anyone to learn how operate the Cable Tester Box. No pre-programming and calibration are required, since this box only checks continuity. 2. Fast: The cable tester box checks all the possible electrical connections in parallel at a push of a button. If a cable normally takes half an hour to test, using the Cable Tester Box will improve the speed to as little as 60 seconds to complete. 3. Versatile: Multiple cable tester boxes can be used together. As long as all the boxes share the same electrical potential, any number of connectors can be tested together.

Lee, Jason H.↗
NASA NTRS1988

A software simulation study of the long constraint length VLSI Viterbi decoder

A software simulation of long constraint length Viterbi decoders was developed. This software closely follows the hardware architecture that was chosen for the Very Large Scale Integration implementation. The program is used to validate the design of the decoder and to generate test vectors for the VLSI circuits.

Arnold, S.↗