The effects of space radiation on MOSFET DEVICES and some application implications of those effects
Space radiation effect on MOSFET devices
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Space radiation effect on MOSFET devices
Fabrication, testing, and implementation of metal oxide field effect transistors in Anchored Interplanetary Monitoring Platform D and E telemetry encoder
Interface problems between plated wire magnetic memory and MOS
Characterization plan for testing of amplifier, micropower, MOS, and dielectrically isolated circuits - space radiation effects on silicon integrated microcircuits
Decontamination of lunar orbiting AIMP-D SPACECRAFT electronic circuit board and MOSFET CIRCUITRY
Piezoresistance and piezo-Hall effect in semiconducting strontium titanium oxide
Tunneling between metal and silicon separated by thin polymer film insulator
Proton irradiation effects in MOS and junction field effect transistors and integrated circuits
Ionizing radiation effects on silicon planar bipolar transistors determine degradation mechanisms
Space radiation effect on MOSFET and metal- silicon nitride-silicon devices, noting protective methods
Exchange model of zero bias tunneling anomalies, discussing Hamiltonian, interference magnetic scattering and metal junctions
Anomalous shift in gate threshold voltage of high transconductance p-channel MOSFETs during exposure to space-like radiation
Effects of electric fields and configurations on thermal annealing and radiation hardening of MOSFETs
Cobalt 60 gamma radiation effect on MOS diodes fabricated on silicon substrates, noting surface state and oxide charge densities
Equivalent circuit and modified and approximate models for metal oxide semiconductor-field effect transistor devices, and adaptability to computerized circuit design
Oxidation of semiconductors and high-temperature superconductors achieved at lower temperatures by use of oxygen molecules or atoms raised into specific excited states. Use of excited oxygen (or other species) of interest in research on kinetics and mechanisms of chemical reactions. Used in ultra-high-vacuum chamber also equipped for such surface-analytical techniques as x-ray photoelectron spectroscopy.
Most of optical and semiconductor single crystalline materials produced in the electronic industry is grown with the Czochralski technique. This is the only technique capable of producing large high quality single crystals in a reasonable amount of time. The technique originated, and took its name, from pioneering work by Polish engineer J. Czochralski in 1917, who pulled single crystal wires (fibers) of low melting point metals from the melt in order to determine the maximum speeds at which they could be crystallized. The technique has been modified and its application has been extended first to the growth of silicon and later to a very wide range of compound semiconductors, metals, oxides and halides. It is now the dominant technique for the wide range of materials in the electronic industries. Czochralski growth is initiated by dipping a seed crystal of a chosen crystallographic orientation onto the surface of a melt contained in the heated crucible. The seed is then slowly withdrawn, solidifying the adherent column of the melt in steady state at an average rate given by the sum of the pulling rate and the rate of lowering the solid-liquid interface due to the depletion of the melt in the crucible. The control of the desired crystal diameter is achieved by closely controlling the heat balance at the solid-liquid interface.
In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.