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At least 325 records · Page 18

A 4 x 4 array module of position-sensitive virtual Frisch-grid CdZnTe detectors for gamma-ray imaging spectrometers

Arrays of position-sensitive virtual Frisch-grid CdZnTe (CZT) detectors offer an economical approach to making high efficiency and high energy resolution gamma cameras for spectroscopy and imaging of radioactive sources. There are many application areas for such instruments including gamma-rays astronomy, medical and industrial imaging, nonproliferation and nuclear safeguards. We present the test results from a 4x4 array module coupled to the front-end ASIC. The array houses 16 detectors made of 6x6x20 mm 3 CZT crystals. Each crystal is encapsulated inside an ultrathin polyester shell and furnished with four 5-mm-wide charge-sensing pads placed near the anode on each side of the detector. The pad’s signals are used to measure X-Y coordinates while the cathode signals give the interaction depths (Z coordinates). Combined together the signals provide 3D position information of the interaction points which can be used to correct the detector response non-uniformity. This allows developers to use standard grade (unselected) CZT crystals while retaining high spectroscopic performance comparable with that of the H3D pixelated detectors. The array’s design provides flexibility to replace individual detectors and extend their sizes, potentially increasing upwards of 4 cm in height. We started development of position-sensitive VFG detectors several years ago and today this technology has reached a high-maturity level and is ready to use in practical applications.

3D charge-loss correction↗

An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.

Hunter, Don J↗

A survey of techniques for optimizing transformer inference

Recent years have seen a phenomenal rise in the performance and applications of transformer neural networks. The family of transformer networks, including Bidirectional Encoder Representations from Transformer (BERT), Generative Pretrained Transformer (GPT) and Vision Transformer (ViT), have shown their effectiveness across Natural Language Processing (NLP) and Computer Vision (CV) domains. Transformer-based networks such as ChatGPT have impacted the lives of common men. However, the quest for high predictive performance has led to an exponential increase in transformers' memory and compute footprint. Researchers have proposed techniques to optimize transformer inference at all levels of abstraction. Further, this paper presents a comprehensive survey of techniques for optimizing the inference phase of transformer networks. We survey techniques such as knowledge distillation, pruning, quantization, neural architecture search and lightweight network design at the algorithmic level. We further review hardware-level optimization techniques and the design of novel hardware accelerators for transformers. We summarize the quantitative results on the number of parameters/FLOPs and the accuracy of several models/techniques to showcase the tradeoff exercised by them. We also outline future directions in this rapidly evolving field of research. We believe that this survey will educate both novice and seasoned researchers and also spark a plethora of research efforts in this field.

97 MATHEMATICS AND COMPUTING↗

Flexible high speed codec

The project's objective is to develop an advanced high speed coding technology that provides substantial coding gains with limited bandwidth expansion for several common modulation types. The resulting technique is applicable to several continuous and burst communication environments. Decoding provides a significant gain with hard decisions alone and can utilize soft decision information when available from the demodulator to increase the coding gain. The hard decision codec will be implemented using a single application specific integrated circuit (ASIC) chip. It will be capable of coding and decoding as well as some formatting and synchronization functions at data rates up to 300 megabits per second (Mb/s). Code rate is a function of the block length and can vary from 7/8 to 15/16. Length of coded bursts can be any multiple of 32 that is greater than or equal to 256 bits. Coding may be switched in or out on a burst by burst basis with no change in the throughput delay. Reliability information in the form of 3-bit (8-level) soft decisions, can be exploited using applique circuitry around the hard decision codec. This applique circuitry will be discrete logic in the present contract. However, ease of transition to LSI is one of the design guidelines. Discussed here is the selected coding technique. Its application to some communication systems is described. Performance with 4, 8, and 16-ary Phase Shift Keying (PSK) modulation is also presented.

Boyd, R. W.↗

Development of Thermal Infrared Sensor to Supplement Operational Land Imager

The thermal infrared sensor (TIRS) is a quantum well infrared photodetector (QWIP)-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 m. The focal plane will contain three 640 ~512 QWIP arrays mounted onto a silicon substrate. The readout integrated circuit (ROIC) addresses each pixel on the QWIP arrays and reads out the pixel value (signal). The ROIC is controlled by the focal plane electronics (FPE) by means of clock signals and bias voltage value. The means of how the FPE is designed to control and interact with the TIRS focal plane assembly (FPA) is the basis for this work. The technology developed under the FPE is for the TIRS focal plane assembly (FPA). The FPE must interact with the FPA to command and control the FPA, extract analog signals from the FPA, and then convert the analog signals to digital format and send them via a serial link (USB) to a computer. The FPE accomplishes the described functions by converting electrical power from generic power supplies to the required bias power that is needed by the FPA. The FPE also generates digital clocking signals and shifts the typical transistor-to-transistor logic (TTL) to }5 V required by the FPA. The FPE also uses an application- specific integrated circuit (ASIC) named System Image, Digitizing, Enhancing, Controlling, And Retrieving (SIDECAR) from Teledyne Corp. to generate the clocking patterns commanded by the user. The uniqueness of the FPE for TIRS lies in that the TIRS FPA has three QWIP detector arrays, and all three detector arrays must be in synchronization while in operation. This is to avoid data skewing while observing Earth flying in space. The observing scenario may be customized by uploading new control software to the SIDECAR.

Shu, Peter↗

Towards Automated Generation of Chiplet-Based Systems

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application- Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a high-level frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frameworks), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This talk will discuss ongoing work on the SODA synthesizer to enable no-human-in-the-loop generation and design space exploration of the chiplets for highly specialized artificial intelligence accelerators. Connecting these highly specialized chiplets to general-purpose cores or programmable accelerators will allow to quickly deploy autonomous systems for scientific discovery.

Limaye, Ankur M.↗

Magnetospheric Atmospheric X-ray Imaging Experiment (MAXIE)

This report summarizes the activities sponsored by the Office of Naval Research for the Magnetospheric Atmospheric X-ray Imaging Experiment (MAXIE). The MAXIE instrument was developed as a joint activity of Lockheed, The Aerospace Corporation, and the University of Bergen, Norway. Lockheed was responsible for the overall management of the program, interfacing with the appropriate government agencies, the overall electrical and mechanical design, flight software, environmental testing, spacecraft integration activities, on orbit checkout, and data processing activities. The Magnetospheric Atmospheric X-ray Imaging Experiment (MAXIE), the ONR 401 experiment, is the first in a new class of satellite-borne remote sensing instruments. The primary innovation is the ability to obtain rapid, sequential, images with high sensitivity of the earth's X ray aurora from a low altitude polar orbiting satellite. These images can be used to identify dynamic temporal variations in the three-dimensional (energy and position) distribution of electron precipitation into the atmosphere. MAXIE was launched on the TIROS NOAA-13 satellite on 9 August 1993. The experiment performed well during its turn-on sequence; however, the spacecraft bus failed on 21 August 1993. New spacebased technologies successfully used in MAXIE were mixed-mode ASIC microcircuits, a zero torque scanning system with associated viscoelastic damping, a paraffin stow release mechanism, a parallel integrating PHA processor, a low noise Si(Li) sensor telescope, and an advanced thermal cooling system. MAXIE's on orbit operation, control of penetrating particle backgrounds, and scientific data indicated good overall performance.

Imhof, W. L.↗

The ePix10k 2-megapixel hard X-ray detector at LCLS

The ePix10ka2M (ePix10k) is a new large area detector specifically developed for X-ray free-electron laser (XFEL) applications. The hybrid pixel detector was developed at SLAC to provide a hard X-ray area detector with a high dynamic range, running at the 120 Hz repetition rate of the Linac Coherent Light Source (LCLS). The ePix10k consists of 16 modules, each with 352 × 384 pixels of 100 µm × 100 µm distributed on four ASICs, resulting in a 2.16 megapixel detector, with a 16.5 cm × 16.5 cm active area and ∼80% coverage. The high dynamic range is achieved with three distinct gain settings (low, medium, high) as well as two auto-ranging modes (high-to-low and medium-to-low). Here the three fixed gain modes are evaluated. The resulting dynamic range (from single photon counting to 10000 photons pixel −1 pulse −1 at 8 keV) makes it suitable for a large number of different XFEL experiments. The ePix10k replaces the large CSPAD in operation since 2011. The dimensions of the two detectors are similar, making the upgrade from CSPAD to ePix10k straightforward for most setups, with the ePix10k improving on experimental performance. The SLAC-developed ePix cameras all utilize a similar platform, are tailored to target different experimental conditions and are designed to provide an upgrade path for future high-repetition-rate XFELs. Here the first measurements on this new ePix10k detector are presented and the performance under typical XFEL conditions evaluated during an LCLS X-ray diffuse scattering experiment measuring the 9.5 keV X-ray photons scattered from a thin liquid jet.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Design and Evaluation of the LAr Trigger Digitizer Board in the ATLAS Phase-I Upgrade

The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) calorimeters will be installed during the second long shutdown of the Large Hadron Collider (LHC) in 2019-2020 which will enable enhanced instantaneous luminosities during LHC Run 3 from 2021 through 2023. In this trigger upgrade, so-called supercells are introduced to provide higher granularity, higher resolution and longitudinal shower shape information from the LAr calorimeters to the Level-1 trigger processors. A new LAr Trigger Digitizer Board (LTDB) will process and digitize up to 320 channels of supercell signals, and transmit them via 40 fiber optical links to the back end where the data are further processed and transmitted to the trigger processors. Five pairs of bidirectional GBT links are used for slow control and monitoring between LTDB and the Front-End LInk eXchange (FELIX) in the ATLAS Trigger and Data Acquisition (TDAQ) system. Here, the LTDB also outputs 64 summed analog legacy signals to the current Tower Builder Board via a new baseplane. A test system for the production of 124 LTDBs has been developed, supporting configuration and calibration of all ASICs

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application-Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frame-works), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This paper provides an overview of the flow in the context of the generation of accelerators for edge processing to be integrated in transmission electron microscopy (TEM) devices, focusing on use cases from precision material synthesis. We show the tool in action with an example of design space exploration for inference on reconfigurable devices with a conventional deep neural network model (LeNet). Finally, we discuss the research directions and opportunities enabled by SODA in the area of autonomous control for scientific experimental workflows.

Castellana, Vito G.↗

NASA Tech Briefs, December 2003

Topics covered include: Organic/Inorganic Hybrid Polymer/Clay Nanocomposites; Less-Toxic Coatings for Inhibiting Corrosion of Aluminum; Liquid Coatings for Reducing Corrosion of Steel in Concrete; Processable Polyimides Containing APB and Reactive End Caps; Rod/Coil Block Copolyimides for Ion-Conducting Membranes; Techniques for Characterizing Microwave Printed Antennas; Cylindrical Antenna With Partly Adaptive Phased-Array Feed; Command Interface ASIC - Analog Interface ASIC Chip Set; Predicting Accumulations of Ice on Aerodynamic Surfaces; Analyzing Aeroelasticity in Turbomachines; Software for Allocating Resources in the Deep Space Network; Expert Seeker; High-Speed Recording of Test Data on Hard Disks; Functionally Graded Nanophase Beryllium/Carbon Composites; Thin Thermal-Insulation Blankets for Very High Temperatures; Aerostructures Test Wing; Flight-Test Evaluation of Flutter-Prediction Methods; Piezoelectrically Actuated Microvalve for Liquid Effluents; Larger-Stroke Piezoelectrically Actuated Microvalve; Innovative, High-Pressure, Cryogenic Control Valve: Short Face-to-Face, Reduced Cost; Safer Roadside Crash Walls Would Limit Deceleration; Improved Interactive Medical-Imaging System; Scanning Microscopes Using X Rays and Microchannels; Slotting Fins of Heat Exchangers to Provide Thermal Breaks; Methane Clathrate Hydrate Prospecting; Automated Monitoring with a BSP Fault-Detection Test; Automated Monitoring with a BCP Fault-Decision Test; Vector-Ordering Filter Procedure for Data Reduction; Remote Sensing and Information Technology for Large Farms; Developments at the Advanced Design Technologies Testbed; Spore-Forming Bacteria that Resist Sterilization; and Acoustical Applications of the HHT Method.

Source record↗

Pressure-Sensor Assembly Technique

Nielsen Engineering & Research (NEAR) recently developed an ultrathin data acquisition system for use in turbomachinery testing at NASA Glenn Research Center. This system integrates a microelectromechanical- systems- (MEMS-) based absolute pressure sensor [0 to 50 psia (0 to 345 kPa)], temperature sensor, signal-conditioning application-specific integrated circuit (ASIC), microprocessor, and digital memory into a package which is roughly 2.8 in. (7.1 cm) long by 0.75 in. (1.9 cm) wide. Each of these components is flip-chip attached to a thin, flexible circuit board and subsequently ground and polished to achieve a total system thickness of 0.006 in. (0.15 mm). Because this instrument is so thin, it can be quickly adhered to any surface of interest where data can be collected without disrupting the flow being investigated. One issue in the development of the ultrathin data acquisition system was how to attach the MEMS pressure sensor to the circuit board in a manner which allowed the sensor s diaphragm to communicate with the ambient fluid while providing enough support for the chip to survive the grinding and polishing operations. The technique, developed by NEAR and Jabil Technology Services Group (San Jose, CA), is described below. In the approach developed, the sensor is attached to the specially designed circuit board, see Figure 1, using a modified flip-chip technique. The circular diaphragm on the left side of the sensor is used to actively measure the ambient pressure, while the diaphragm on the right is used to compensate for changes in output due to temperature variations. The circuit board is fabricated with an access hole through it so that when the completed system is installed onto a wind tunnel model (chip side down), the active diaphragm is exposed to the environment. After the sensor is flip-chip attached to the circuit board, the die is underfilled to support the chip during the subsequent grinding and polishing operations. To prevent this underfill material from getting onto the sensor s diaphragms, the circuit board is fabricated with two 25- micrometer-tall polymer rings, sized so that the diaphragms fit inside the rings once the chip is attached.

Pruzan, Daniel A.↗

Digital control of magnetic bearings in a cryogenic cooler

This paper describes the design of a digital control system for control of magnetic bearings used in a spaceborne cryogenic cooler. The cooler was developed by Philips Laboratories for the NASA Goddard Space Flight Center. Six magnetic bearing assemblies are used to levitate the piston, displacer, and counter-balance of the cooler. The piston and displacer are driven by linear motors in accordance with Stirling cycle thermodynamic principles to produce the desired cooling effect. The counter-balance is driven by a third linear motor to cancel motion induced forces that would otherwise be transmitted to the spacecraft. An analog control system is currently used for bearing control. The purpose of this project is to investigate the possibilities for improved performance using digital control. Areas for potential improvement include transient and steady state control characteristics, robustness, reliability, adaptability, alternate control modes, size, weight, and cost. The present control system is targeted for the Intel 80196 microcontroller family. The eventual introduction of application specific integrated circuit (ASIC) technology to this problem may produce a unique and elegant solution both here and in related industrial problems.

Feeley, J.↗

Robustness of the smartpixels classifier for different simulated sensor geometries and non-ideal detector conditions

Pixel tracking detectors at upcoming collider experiments will see unprecedented charged-particle densities. Real-time data reduction on the detector will enable higher granularity and faster readout, possibly enabling the use of the pixel detector in high-rate online event selection, such as the ATLAS or CMS first-level trigger systems. This data reduction can be accomplished with a neural network (NN) in the readout chip bonded with the sensor that recognizes and rejects tracks with low transverse momentum (p T ) based on the geometrical shape of the charge deposition (“cluster”). To design viable detectors for deployment, the dependence of the NN as a function of the sensor geometry, external magnetic field, irradiation, and noise must be understood. In this paper, we present first studies of the efficiency and data reduction for planar pixel sensors exploring these parameters. For the CMS HL-LHC sensor geometry, we obtain a signal efficiency of (91.9 ± 0.7)% and a data reduction of (29.7 ± 1.0)%. A smaller sensor pitch in the bending direction improves the p T discrimination, but a larger pitch can be partially compensated with detector thickness. Any accumulated radiation damage also changes the cluster shape, reducing the signal efficiency compared to the baseline by approximately 30–60% in absolute terms, but nearly all of the performance can be recovered through retraining of the network and updating the weights. Finally, the impact of noise was investigated, and retraining the network on noise-injected datasets was found to maintain performance within 6% of the baseline network trained and evaluated on noiseless data. •ASIC-compatible track-momentum classifier is robust in realistic detector conditions.•About 90% signal efficiency and 30% data reduction per layer for CMS HL-LHC geometry.•Single-layer signal efficiency increases for smaller pixel pitch or thicker sensors.•Performance with noise or after radiation damage mostly recovered by retraining.

Shekar, Danush [Illinois U., Chicago] (ORCID:00000↗

X-Ray Detector Research at MSFC for Space Applications

NASA's Vision for Space Exploration has specific goals aimed at exploring the Solar System. This vision, under presidential mandate includes landing humans on the moon before the end of the next decade, paving the way for eventual journeys to Mars and beyond. The first missions to the moon will be in the form of both Orbiters and Landers, with the goal of paving the way for human return. One of the instruments we are currently working on,in collaboration with Brookhaven National Laboratory, is a lunar orbiter fluorescent x-ray spectrometer to finely map the light elements (down to Carbon) on surface of the moon. Funded NASA s Planetary Instrument Definition and Development Program the instrument is based on silicon drift detector arrays read out by custom ASICs. These offer the promise of high spectral resolution, necessary for resolving weak lines against a strong background continuum, and very low power requirements, necessary for large areas (greater than 500 square centimeters) required for future lunar missions. Further, the inherent radiation hardness of these detectors makes them ideal candidates for exploring the Jovian system, where the harsh radiation environment from Jupiter s radiation belts creates unfavorable detector conditions. Looking beyond our solar system, in the hard x-ray regime (20-80keV.), we are studying Cadmium-Zinc-Telluride pixilated detectors as feasible candidates for focal plane detectors of a hard x-ray telescope. This energy region bridges the gap between thermal and non-thermal x-ray emission from astronomical sources, will allow us to better understand supernovae nucleosynthesis (such as through the Ti-44 lines at 68keV and 78keV), Active Galactic Nuclei and other compact objects, more completely. The detectors that we are characterizing are 2mm in thickness and are pixilated with a 16x16 array of 300 micrometer pitch pixels (50micometer gap). These detectors are designed at Rutherford Appleton Laboratory, material is from eV Products, and polymer flip-chip assembly was performed by a commercial vendor. An energy resolution of 2.0% at 60keV (or better) should allow us to sufficiently distinguish lines of interest from background continuum, and the detector spatial resolution should be fine enough to over-sample the focal spot from the x-ray focusing optics by about a factor of two. Full technical details of these developments will be presented.

Gaskin, Jessica↗

Heterogeneous Integration, An Approach to High Density and High Flexibility Electronic Packaging

Key to the design of spacecraft for exploration of the outer planets will be the development of highly integrated and mass/volume efficient electronic systems. Exploration of the outer planets will require optimized propulsion approaches which mandates mass minimization. If one looks at a mission such as the Europa Lander, a high mass/volume efficiency feeds back directly into lower mass for radiation shielding. Concurrently the long mission lengths will drive the need for fault isolation and fault tolerance. The ability to build distributed electronic systems is an inherent requirement and one which is enabled by heterogeneous integration. The electronic packaging approach must be capable of interconnecting various components at a scale comparable with that on the components themselves (chip scale) and it must facilitate efficient integration of the electronics with elements of the spacecraft such as structure or antennae. The concept of 'Heterogeneous Integration' is being explored in the System On A Chip (SOAC) Project at JPL. The goal, of this approach to electronic packaging, is to enable the fabrication and assembly of complete electronic subsystems from components fabricated by a range of processes. Included in such a system could be MEMS sensors, SOI mixed signal ASICs, micro scale passive components and micro power. Secondarily the compact size will enable distributed architectures and integrated assemblies. Additional information is contained in the original extended abstract.

DAgostino, S. A.↗

An Integrated MEMS Sensor Cluster System for Aerospace Applications

Efforts to reduce viscous drag on airfoils could results in a considerable saving for the operation of flight vehicles including those of space transportation. This reduction of viscous drag effort requires measurement and active control of boundary layer flow property on an airfoil. Measurement of viscous drag of the boundary layer flow over an airfoil with minimal flow disturbance is achievable with newly developed MEMS sensor clusters. These sensor clusters provide information that can be used to actively control actuators to obtain desired flow properties or design a vehicle to satisfy particular boundary layer flow criteria. A series of MEMS sensor clusters has been developed with a data acquisition and control module for local measurements of shear stress, pressure, and temperature on an airfoil. The sensor cluster consists of two shear stress sensors, two pressure sensors, and two temperature sensors on a surface area of 1.24 mm x 1.86 mm. Each sensor is 300 microns square and is placed on a flexible polyimide sheet. The shear stress sensor is a polysilicon hot-film resistor, which is insulated by a vacuum cavity of 200 x 200 x 2 microns. The pressure sensors are silicon piezoresistive type, and the temperature sensors are also hot film polysilicon resistors. The total size of the cluster including sensors and electrical leads is 1 Omm x 1 Omm x 0.1 mm. A typical sensitivity of shear stress sensor is 150 mV/Pascal, the pressure sensors are an absolute type with a measurement range from 9 to 36 psia with 0.8mV/V/psi sensitivity, and the temperature sensors have a measurement resolution of 0.1 degree C. The sensor clusters are interfaced to a data acquisition and control module that consists of two custom ASICs (Application Specific Integrated Circuits) and a micro-controller. The data acquisition and control module transfers data to a host PC that configures and controls a total of three sensor clusters. Functionality of the entire system has been tested in the laboratory, and preliminary test results are presented.

Kahng, Seun↗