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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Effect of Soluble Corrosion Products on Electrical Double Layer in LiCl-KCl Molten Salts

Corrosion in molten salts greatly hampers the application for renewable energy applications like molten salt reactors. To develop effective strategies for corrosion mitigation, understanding the interfacial structures and properties such as specific ion adsorption and electrical double layer capacitance are crucial. Using cyclic voltammetry and electrochemical impedance spectroscopy, we systematically studied the interfaces on various model electrodes including W (solid), Bi (liquid), and the stainless steel 316 in LiCl-KCl eutectic molten salts with the addition of corrosion species CrCl 2 and FeCl 2 . Both Cr 2+ and Fe 2+ ions increased electrical double layer capacitance, with Cr 2+ showing specific adsorption behavior and shifting the potential of zero charge, while Fe 2+ had minimal effect on point of zero charge. Two-working electrode measurements revealed increasing open-circuit potential and electrical double layer capacitance during the exposure of stainless steel 316, indicating its progressive corrosion and ion accumulation at the interface. X-ray photoelectron spectroscopy and Raman confirmed Cr enrichment at the interface. This work highlights the strong correlation between electrical double layer behavior and corrosion dynamics in molten salts and suggests electrical double layer capacitance as a sensitive, in situ indicator for corrosion monitoring.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2024

Microfabricated Ion Traps on Sapphire for Larger Trap Areas and Higher Qubit Count

Surface ion traps are a promising platform for quantum computing due to their potential to store large numbers of ions that can be addressed by electrical and optical control signals in order to implement quantum algorithms. Increasing the power of the quantum computer requires increasing the number of ions, but this poses a significant challenge in that it leads to a non-linear increase in on-chip power dissipation. The primary contributor to this power scaling in current devices is the capacitance between the radio frequency (RF) electrode and the metal plane that shields the silicon substrate from the RF signals applied to it. Silicon has traditionally been chosen for the substrate material for compatibility with the processing required for multi-metal-level traps. In this work, we address these capacitance and fabrication challenges by replacing the commonly used silicon substrate with an insulating sapphire substrate to fabricate a multi-metal-level ion trap, while still employing common semiconductor manufacturing techniques. This change in substrate allows the design to remove the metal shielding from the device design, reducing the capacitance of the RF electrode. The electrical characteristics of these traps were measured, specifically trap impedance, capacitance, and voltage breakdown, and compared to nearly identical silicon trap devices. Finally, we used laser cutting techniques to shape a sapphire wafer into bowtie shapes matching silicon traps previously fabricated at Sandia National Labs to explore solutions for integrating sapphire substrates into non-rectangular ion trap designs.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1976

Rapid and precise measurement of flatband voltage

The paper outlines the design, principles of operation, and calibration of a five-IC network intended to give a rapid, precise, and automatic determination of the flatband voltage of MOS capacitors. The basic principle of measurement is to compare the analog output voltage of a capacitance meter - which is directly proportional to the capacitance being measured - with a preset or dialed-in voltage proportional to the calculated flatband capacitance by means of a comparator circuit. The bias to the MOS capacitor supplied through the capacitance meter is provided by a ramp voltage going from a negative toward a positive voltage level and vice versa. The network employs two monostable multivibrators for reading and recording the flatband voltage and for resetting the initial conditions and restarting the ramp. The flatband voltage can be held and read on a digital voltmeter.

Li, S. P.↗
NASA NTRS1976

Metal-insulator-semi-conductor studies of lead telluride

The capacitance and conductance-voltage characteristics were measured on metal-insulator-semiconductor capacitors fabricated with zirconium dioxide films on single-crystal lead telluride. At 77 K, on both n- and p-type substrates, evidence of surface potential control was obtained. Comparison of the measured capacitance-voltage characteristics with those calculated from the equilibrium solution of the one-dimensional Poisson equation indicated qualitative agreement, although the slope of the measured capacitance in the region near the capacitance minimum was less steep than calculated.

Lilly, D. A.↗
NASA NTRS1991

Advanced Langmuir Probe (LP)

The dynamic response of the MK-2 version of the Langmuir probe amplifier was studied. The settling time of the step response is increased by: (1) stray node-to-ground capacitance at series connections between high value feedback resistors; and (2) input capacitance due to the input cable, FET switches, and input source follower. The stray node-to-ground capacitances can be reduced to tolerable levels by elevating the string of feedback resistors above the printing board. A new feedback network was considered, with promising results. The design uses resistances having much lower nominal values, thereby minimizing the effect of stray capacitances. Faster settling times can be achieved by using an operational amplifier having a higher gain-bandwidth product.

Voronka, N. R.↗
NASA NTRS1993

New experimental techniques for solar cells

Solar cell capacitance has special importance for an array controlled by shunting. Experimental measurements of solar cell capacitance in the past have shown disagreements of orders of magnitude. Correct measurement technique depends on maintaining the excitation voltage less than the thermal voltage. Two different experimental methods are shown to match theory well, and two effective capacitances are defined for quantifying the effect of the solar cell capacitance on the shunting system.

Lenk, R.↗
NASA NTRS1993

Delay analysis of combinations of pass transistors and classical logic gates

Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.

Gibson, Jonathan S.↗
NASA NTRS1995

High input impedance amplifier

High input impedance amplifiers are provided which reduce the input impedance solely to a capacitive reactance, or, in a somewhat more complex design, provide an extremely high essentially infinite, capacitive reactance. In one embodiment, where the input impedance is reduced in essence, to solely a capacitive reactance, an operational amplifier in a follower configuration is driven at its non-inverting input and a resistor with a predetermined magnitude is connected between the inverting and non-inverting inputs. A second embodiment eliminates the capacitance from the input by adding a second stage to the first embodiment. The second stage is a second operational amplifier in a non-inverting gain-stage configuration where the output of the first follower stage drives the non-inverting input of the second stage and the output of the second stage is fed back to the non-inverting input of the first stage through a capacitor of a predetermined magnitude. These amplifiers, while generally useful, are very useful as sensor buffer amplifiers that may eliminate significant sources of error.

Kleinberg, Leonard L.↗
NASA NTRS2005

Variable electronic shutter in CMOS imager with improved anti smearing techniques

A leakage compensated snapshot imager provides a number of different aspects to prevent smear and other problems in a snapshot imager. The area where the imager is formed may be biased in a way that prevents photo carriers including electrons and holes from reaching a storage area. In addition, a number of different aspects may improve the efficiency. The capacitance per unit area of the storage area may be one, two or more orders of magnitude greater than the capacitance per-unit area of the photodiode. In addition, a ratio between photodiode capacitance and storage area capacitance is maintained larger than 0.7.

Pain, Bedabrata↗
NASA NTRS1977

Ferroelectric liquid crystal display

A ferroelectric liquid crystal display device employs capacitance spoiling layers to minimize unneeded capacitances created by crossovers of X and Y address lines and to accurately define desired capacitances. The spoiler layers comprise low dielectric constant layers which space electrodes from the ferroelectric at crossover points where capacitance is not needed for device operation.

York, Paul K.↗
NASA NTRS2007

Increasing Linear Dynamic Range of a CMOS Image Sensor

A generic design and a corresponding operating sequence have been developed for increasing the linear-response dynamic range of a complementary metal oxide/semiconductor (CMOS) image sensor. The design provides for linear calibrated dual-gain pixels that operate at high gain at a low signal level and at low gain at a signal level above a preset threshold. Unlike most prior designs for increasing dynamic range of an image sensor, this design does not entail any increase in noise (including fixed-pattern noise), decrease in responsivity or linearity, or degradation of photometric calibration. The figure is a simplified schematic diagram showing the circuit of one pixel and pertinent parts of its column readout circuitry. The conventional part of the pixel circuit includes a photodiode having a small capacitance, CD. The unconventional part includes an additional larger capacitance, CL, that can be connected to the photodiode via a transfer gate controlled in part by a latch. In the high-gain mode, the signal labeled TSR in the figure is held low through the latch, which also helps to adapt the gain on a pixel-by-pixel basis. Light must be coupled to the pixel through a microlens or by back illumination in order to obtain a high effective fill factor; this is necessary to ensure high quantum efficiency, a loss of which would minimize the efficacy of the dynamic- range-enhancement scheme. Once the level of illumination of the pixel exceeds the threshold, TSR is turned on, causing the transfer gate to conduct, thereby adding CL to the pixel capacitance. The added capacitance reduces the conversion gain, and increases the pixel electron-handling capacity, thereby providing an extension of the dynamic range. By use of an array of comparators also at the bottom of the column, photocharge voltages on sampling capacitors in each column are compared with a reference voltage to determine whether it is necessary to switch from the high-gain to the low-gain mode. Depending upon the built-in offset in each pixel and in each comparator, the point at which the gain change occurs will be different, adding gain-dependent fixed pattern noise in each pixel. The offset, and hence the fixed pattern noise, is eliminated by sampling the pixel readout charge four times by use of four capacitors (instead of two such capacitors as in conventional design) connected to the bottom of the column via electronic switches SHS1, SHR1, SHS2, and SHR2, respectively, corresponding to high and low values of the signals TSR and RST. The samples are combined in an appropriate fashion to cancel offset-induced errors, and provide spurious-free imaging with extended dynamic range.

Pain, Bedabrata↗
NASA NTRS2014

Dielectric Performance of a High Purity HTCC Alumina at High Temperatures - a Comparison Study with Other Polycrystalline Alumina

A very high purity (99.99+%) high temperature co-fired ceramic (HTCC) alumina has recently become commercially available. The raw material of this HTCC alumina is very different from conventional HTCC alumina, and more importantly there is no glass additive in this alumina material for co-firing processing. Previously, selected HTCC and LTCC (low temperature co-fired ceramic) alumina materials were evaluated at high temperatures as dielectric and compared to a regularly sintered 96% polycrystalline alumina (96% Al2O3), where 96% alumina was used as the benchmark. A prototype packaging system based on regular 96% alumina with Au thickfilm metallization successfully facilitated long term testing of high temperature silicon carbide (SiC) electronic devices for over 10,000 hours at 500 C. In order to evaluate this new high purity HTCC alumina for possible high temperature packaging applications, the dielectric properties of this HTCC alumina substrate were measured and compared with those of 96% alumina and a previously tested LTCC alumina from room temperature to 550 C at frequencies of 120 Hz, 1 KHz, 10 KHz, 100 KHz, and 1 MHz. A parallel-plate capacitive device with dielectric of the HTCC alumina and precious metal electrodes were used for measurements of the dielectric constant and dielectric loss of the co-fired alumina material in the temperature and frequency ranges. The capacitance and AC parallel conductance of the capacitive device were directly measured by an AC impedance meter, and the dielectric constant and parallel AC conductivity of the dielectric were calculated from the capacitance and conductance measurement results. The temperature and frequency dependent dielectric constant, AC conductivity, and dissipation factor of the HTCC alumina substrate are presented and compared to those of 96% alumina and a selected LTCC alumina. Other technical advantages of this new co-fired material for possible high packaging applications are also discussed.

Electronic packaging↗
NASA NTRS2012

Dielectric Performance of High Purity HTCC Alumina at High Temperatures - A Comparison Study with Other Polycrystalline Alumina

A very high purity (99.99+) high temperature co-fired ceramic (HTCC) alumina has recently become commercially available. The raw material of this HTCC alumina is very different from conventional HTCC alumina, and more importantly there is no glass additive in this co-fired material. Previously, selected HTCC and LTCC (low temperature co-fired ceramic) alumina materials were evaluated at high temperatures as dielectric and compared to a regularly sintered 96 polycrystalline alumina (96 Al2O3), where 96 alumina was used as the benchmark. A prototype packaging system based on regular 96 alumina with Au thick-film metallization successfully facilitated long term testing of high temperature silicon carbide (SiC) electronic devices for over 10,000 hours at 500C. In order to evaluate this new HTCC alumina for possible high temperature packaging applications, the dielectric properties of this HTCC alumina substrate were measured and compared with those of 96 alumina and a LTCC alumina from room temperature to 550C at frequencies of 120 Hz, 1 KHz, 10 KHz, 100 KHz, and 1 MHz. A parallel-plate capacitive device with dielectric of the HTCC alumina and precious metal electrodes were used for measurements of the dielectric constant and dielectric loss of the co-fired alumina material in the temperature and frequency ranges. The capacitance and AC parallel conductance of the capacitive device were directly measured by an AC impedance meter, and the dielectric constant and parallel AC conductivity of the dielectric were calculated from the capacitance and conductance measurement results. The temperature and frequency dependent dielectric constant, AC conductivity, and dissipation factor of the HTCC alumina substrate are presented and compared to those of 96 alumina. Other technical advantages of this new co-fired material for possible high packaging applications are also discussed.

High temperature↗
NASA NTRS2016

Carbon Nanotube Tape Vibrating Gyroscope

A vibrating gyroscope includes a piezoelectric strip having length and width dimensions. The piezoelectric strip includes a piezoelectric material and carbon nanotubes (CNTs) substantially aligned and polled along the strip's length dimension. A spindle having an axis of rotation is coupled to the piezoelectric strip. The axis of rotation is parallel to the strip's width dimension. A first capacitance sensor is mechanically coupled to the spindle for rotation therewith. The first capacitance sensor is positioned at one of the strip's opposing ends and is spaced apart from one of the strip's opposing faces. A second capacitance sensor is mechanically coupled to the spindle for rotation therewith. The second capacitance sensor is positioned at another of the strip's opposing ends and is spaced apart from another of the strip's opposing faces. A voltage source applies an AC voltage to the piezoelectric strip.

Tucker, Dennis Stephen↗
DOE OSTI2026

Predicting critical heat flux using localized sensing at invisible vapor-liquid interfaces

Predicting critical heat flux (CHF) in two-phase electronics cooling systems remains a significant challenge due to the sudden onset of boiling crisis and the difficulty in directly visualizing vapor-liquid interfaces. Existing sensing methods rely on lagging temperature measurements, optically accessible systems, or spatially averaged signals that cannot pinpoint CHF initiation at localized high-heat-flux regions. Here, we report a planar capacitive sensing approach that enables real-time, localized detection of vapor-liquid interface dynamics for CHF prediction in boiling heat transfer. The capacitive sensor exploits the dielectric constant difference between liquid and vapor phases to capture bubble nucleation, growth, and departure dynamics with a temporal resolution down to 2 ms. The capacitive sensing reveals distinct signals across boiling regimes: from high-frequency fluctuations during strong nucleate boiling to low-frequency fluctuations with increased amplitudes when approaching CHF. The multi-sensor array experiments demonstrate real-time localized sensing, where each sensor responds exclusively to boiling in its immediate vicinity without crosstalk from neighboring regions. This non-intrusive sensing approach provides predictive rather than lagging sensing signals of CHF occurrence, offering predictive diagnosis of two-phase liquid cooling for the thermal management of high-power-density electronics.

CHF↗
DOE OSTI2025

Vertically Aligned Carbon Nanotubes Grown on Copper Foil as Electrodes for Electrochemical Double Layer Capacitors

This study reports a binder-free, catalyst-free method for fabricating vertically aligned carbon nanotubes (VACNTs) directly on copper (Cu) foil using plasma-enhanced chemical vapor deposition (PECVD) for electrochemical double-layer capacitor (EDLC) applications. This approach eliminates the need for catalyst layers, polymeric binders, or substrate pre-treatments, simplifying electrode design and enhancing electrical integration. The resulting VACNTs form a dense, uniform, and porous array with strong adhesion to the Cu substrate, minimizing contact resistance and improving conductivity. Electrochemical analysis shows gravimetric specific capacitance (C grav ) and areal specific capacitance (C areal ) of 8 F g −1 and 3.5 mF cm −2 at a scan rate of 5 mV/s, with low equivalent series resistance (3.70 Ω) and charge transfer resistance (0.48 Ω), enabling efficient electron transport and rapid ion diffusion. The electrode demonstrates excellent rate capability and retains 92% of its initial specific capacitance after 3000 charge–discharge cycles, indicating strong cycling stability. These results demonstrate the potential of directly grown VACNT-based electrodes for high-performance EDLCs, particularly in applications requiring rapid charge–discharge cycles and sustained energy delivery.

25 ENERGY STORAGE↗
NASA NTRS2011

Development of Sample Verification System for Sample Return Missions

This paper describes the development of a proof of-concept sample verification system (SVS) for in-situ mass measurement of planetary rock and soil sample in future robotic sample return missions. Our proof-of-concept SVS device contains a 10 cm diameter pressure sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in proximity to an opposing substrate with a narrow gap. The deformation of the membrane makes the gap to be narrower, resulting in increased capacitance between the two nearly parallel plates. Capacitance readout circuitry on a nearby printed circuit board (PCB) transmits data via a low-voltage differential signaling (LVDS) interface. The fabricated SVS proof-of-concept device has successfully demonstrated approximately 1pF/gram capacitance change

Electrodes↗
DOE OSTI2026

Electrochemical Modeling of PID Leakage Current of PV Modules: Steady-State Current, Transient Current, and RC-Equivalent Circuit

Potential-induced degradation (PID) remains a significant reliability concern for photovoltaic (PV) modules, arising when a voltage difference between the module frame and the solar cells drives unintended leakage current through the glass-encapsulant stack. Although PID ultimately manifests as PID-s, PID-p, or PID-c, the underlying behavior of the leakage current-its magnitude and time dependence-requires clearer electrochemical interpretation. Traditional explanations attribute the initial transient current to bulk capacitive elements of the glass, encapsulant, and antireflection coatings, and the steady-state current according to their effective ohmic resistance. More recent studies, however, indicate that electrochemical charge-transfer processes at the encapsulant-metallization interface can play a dominant role in defining the leakage-current path. This paper develops a unified electrochemical framework for modeling PID leakage current. First, an RC-equivalent circuit is formulated by combining conventional RC elements with a Randles-type interface to capture transient leakage current through double-layer capacitance and faradaic processes at ionic-electronic boundaries. Second, the steady-state current-voltage behavior is explained using a linearized Butler-Volmer relationship, showing that the measured ohmic response corresponds to the low-overpotential limit of charge-transfer kinetics. Analytical results demonstrate that, for typical module materials-3.2-mm soda-lime glass and 0.45-mm encapsulant-the dominant modulators to PID leakage current are the glass surface resistance (under dry-surface conditions), the glass bulk capacitance, and the encapsulant resistance (under wet-surface conditions), with soda lime glass surface and EVA/POE encapsulant resistances primarily governing steady-state current. The proposed electrochemical model is validated against measured leakage-current data, showing good agreement in both the magnitude and the time-dependent evolution of PID leakage current.

14 SOLAR ENERGY↗