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The detailed logic flow for the Flight Design System Executive is presented. The system is designed to provide the hardware/software capability required for operational support of shuttle flight planning.
Quicklist, a preprocessor for an existing wire list program that cuts the description of the wire list by about 67 percent over previous methods, is described. Quicklist uses two different methods to shorten the input data. The first of these is the use of parentheses to allow a compact way of describing signal names which increment (or decrement) by one, i.e., typical signal names in a bus. The other method used is the equal sign. Using this symbol in a signal list says that the rest of the signals on that chip are the same as those on the previous chip described. Quicklist is intended to be the basis of a computer aided logic design system.
A recent result shows that, for a certain class of systems, the interdependency among the elements of such a system together with the elements constitutes a mathematical structure a partially ordered set. It is called a loop free logic model of the system. On the basis of an intrinsic property of the mathematical structure, a characterization of system component failure in terms of maximal subsets of bad test signals of the system was obtained. Also, as a consequence, information concerning the total number of failure components in the system was deduced. Detailed examples are given to show how to restructure real systems containing loops into loop free models for which the result is applicable.
Two labeling procedures were developed which identify various agricultural crops through the use of Landsat data. One procedure separates barley from other spring small grains, and the other identifies corn and soybeans. For both procedures, a minimum data set (critical acquisition time) has been designated. Landsat data in both image format and various graphic displays were used along with ancillary data to obtain information which aided in labeling the spectral signatures. The corn and soybean procedure also employed a structured decision logic. Test results for the barley separation procedure emphasized the importance of obtaining a critical acquisition and showed some success especially in areas where spring crops followed the expected growth patterns. Two tests of the corn and soybean procedure produced good labeling accuracies. Problems with the procedure were easy to identify, and some solutions were implemented for the second test. Automation of various parts of the procedure and extension to other crops and regions were recommended.
Two integrated circuits, BCD-to-decimal decoder and four-input NAND gate, form basic four, input XOR circuit. Multiple-input exclusive-OR logic is implemented by combining several basic elements. 16-input XOR gate is assembled from five NAND gates and five decoders. Same principle extended to handle more inputs.
The development and testing of an analysis procedure which was developed to improve the consistency and objectively of crop identification using Landsat data is described. The procedure was developed to identify corn and soybean crops in the U.S. corn belt region. The procedure consists of a series of decision points arranged in a tree-like structure, the branches of which lead an analyst to crop labels. The specific decision logic is designed to maximize the objectively of the identification process and to promote the possibility of future automation. Significant results are summarized.
The implementation of DDLTRN and DDLSIM programs on SEL-2 computer system is reported. These programs were tested with DDL descriptions of various complexity. An algorithm to synthesize the combinational logic using the cells available in the standard IC cell library was formulated. The algorithm is implemented as a FORTRAN program and a description of the program is given.
Large-scale integrated (LSI) devices fabricated with integrated injection logic (I2L) were studied by both heavy ion experiments and device analysis to determine the upset threshold, the charge collection volumes and ultimately the probability for upset in the galactic cosmic ray spectrum. The devices studied, the SEP9900A, the SBP9989 and the P-Code generator were fabricated by Texas Instruments, Inc.
Simple modification of oscilloscope probe allows easy detection of floating inputs or tristate outputs in digital-IC's. Oscilloscope probe easily modified with 1/4 W resistor and switch for detecting floating inputs in CMOS logic circuits.
Control signals for phase-delay rectifiers, which require a variable firing angle that ranges from 0 deg to 180 deg, are derived from line-to-line 3-phase signals and both positive and negative firing angle control signals which are generated by comparing current command and actual current. Line-to-line phases are transformed into line-to-neutral phases and integrated to produce 90 deg phase delayed signals that are inverted to produce three cosine signals, such that for each its maximum occurs at the intersection of positive half cycles of the other two phases which are inputs to other inverters. At the same time, both positive and negative (inverted) phase sync signals are generated for each phase by comparing each with the next and producing a square wave when it is greater. Ramp, sync and firing angle controls signals are than used in combinational logic to generate the gate firing control signals SCR gate drives which fire SCR devices in a bridge circuit.
This paper deals with the issue of designing microprocessor based systems with testability in mind. The ease of eventual testability should be a design consideration from the earliest design stage. Design guidelines with explicit examples for ease of testability are given. The issue of testing microprocessors as contrasted with testing random logic design is addressed, and procedures are delineated for the testability of microprocessors. Microprocessor testability design guidelines are discussed both at the design stage of the microprocessor itself as well as at the stage where the processor is imbedded as a component in a larger system. Specific instances and examples of a collection of design do's and don'ts are provided.
Unit-delay simulation, event driven simulation, zero-delay simulation, simulation techniques, 2-valued versus multivalued logic, network initialization, gate operations and alternate network representations, parallel versus serial mode simulation fault modelling, extension of multiprocessor systems, and simulation timing are discussed. Functional level networks, gate equivalent circuits, the prototype BDX-930 network model, fault models, identifying detected faults for BGLOSS are discussed. Preprocessor tasks, postprocessor tasks, executive tasks, and a library of bliss coded macros for GGLOSS are also discussed.
Circuit for checking two-line complementary-logic bits for single faults used as building block for self-checking memory interface for Hammingcoded data. Intended for such applications as fault-tolerant computing, data handling, and data transmission. Circuit performs exclusive-OR function. Many such circuits combined produce complete memory interface with both detection and correction abilities.
Subjects were required to discover the structure of a logical network whose links were invisible. Network structure had to be inferred from the behavior of the components after a failure. It was hypothesized that since such failure diagnosis tasks often draw on spatial processes, a good deal of spatial complexity in the network should affect network discovery. Results show that the ability to discover the linkages in the network is directly related to the spatial complexity of the pathway described by the linkages. This effect was generally independent of the amount of evidence available to subjects about the existence of the link. These results raise the question of whether inferences about spatially complex pathways were simply not made, or whether they were made but not retained because of a high load on memory resources.
Improvements were made to the Adaptive Maneuvering Logic (AML) computer program, a computer-generated, air-to-air combat opponent. The primary improvement was incorporating a measure of performance, the exchange ratio, defined as the statistical measure of number of enemy kills divided by number of friendly losses. This measure was used to test a new modification of the AML's combat tactics. When the new version of the AML competed against the old version, the new version won with an exchange ratio of 1.4.
A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
The nonlinear phenomena of signal beam saturation, pump beam depletion, and optically controlled coupling coefficient of two-beam interaction in photorefractive materials are analyzed. Applications of these phenomena to digital logic operations is discussed and supported by experimental results obtained in photorefractive BaTiO3.
The Adaptive Maneuvering Logic (AML) computer program simulates close-in, one-on-one air-to-air combat between two fighter aircraft. Three important improvements are described. First, the previously available versions of AML were examined for their suitability as a baseline program. The selected program was then revised to eliminate some programming bugs which were uncovered over the years. A listing of this baseline program is included. Second, the equations governing the motion of the aircraft were completely revised. This resulted in a model with substantially higher fidelity than the original equations of motion provided. It also completely eliminated the over-the-top problem, which occurred in the older versions when the AML-driven aircraft attempted a vertical or near vertical loop. Third, the requirements for a versatile generic, yet realistic, aircraft model were studied and implemented in the program. The report contains detailed tables which make the generic aircraft to be either a modern, high performance aircraft, an older high performance aircraft, or a previous generation jet fighter.