Search NASA⌕ Search

SEARCH · Search NASA

Results for “Power MOSFET”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

313 records · Page 18
All sourcesNASA NTRSDOE OSTI
NASA NTRS2019

Design of Low Inductance Busbar for 500 kVA Three-Level ANPC Converter

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active natural clamped converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic cancelling effect, and DC-link capacitor placement. The loop inductance of the designed busbar is verified with simulation, impedance measurements and converter experiment. The results can match with each other and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

SiC MOSFET↗
DOE OSTI2021

Computational Fermi Level Engineering and Doping-Type Conversion of Ga2O3 Via Three-Step Processing

Ga2O3 is being actively explored for power electronics, and other applications due to its ultra- wide bandgap and low projected fabrication cost of high-quality crystals. N-type doping of Ga2O3 can be achieved and tuned, but p-type doping faces fundamental obstacles. Successful engineering of Ga2O3 based devices requires critical control of doping density, Fermi level position, providing opportunities for predictive process simulation. We use first-principles defect equilibrium calculations to simulate a 3-step growth- annealing-quench protocol for hydrogen assisted Mg doping in Ga2O3, taking into account the hydrogen- oxygen-water gas phase equilibrium. We predict type conversion to a net p-type regime following O-rich annealing after growth under reducing conditions in the presence of H2. We show that there is an optimal temperature that maximizes the net acceptor density during the equilibrium annealing step for a given Mg doping level. Quenching of non-equilibrium annealed samples then results in a Fermi level EF below mid-gap down to about EV +1.5 eV, creating a significant number of uncompensated neutral MgGa0 acceptors. This type converted Ga2O3 can create significant built-in field in a p-n junction with an adjoining n-type material and could enable vertical MOSFETs.

CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS,M↗
NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗
DOE OSTI2023

Stacking Faults Originating from Star-Defects in 4H-SiC

Intense efforts are currently in progress to study various sources of basal plane dislocations (BPDs) in SiC epitaxial layers. BPDs can generate Shockley-type stacking faults (SSFs) in SiC epitaxial layers, which have been shown to be associated with the degradation of power devices. This study shows that the star-shaped defect can be a source of several BPDs in the epitaxial layer. We investigate the complex microstructure of the star defect, the generation of BPDs, and expansion of SSFs using various complementary microscopy and optical techniques. We show direct evidence that star-defects can be a nucleation point of single-SSFs that can expand at the core of the defect. Newly found secondary dislocation arrays extending over a few centimeters away are found to be emanating from the primary arms of the star defect. The presence of such dislocation walls and the expansion of single-SSFs will affect the yield of numerous die on a wafer. Further understanding of the formation mechanism of stacking faults generated from star-defects as provided in this study helps understand their effect on SiC-based devices, which is crucial to assess device reliability.

36 MATERIALS SCIENCE↗
NASA NTRS2024

X-57 Maxwell High Lift Motor Controller Electromagnetic Interference Test Results

During research and development for NASA’s X-57 Maxwell all-electric aircraft project, the efficiency and power density requirements of its electric propulsion subsystem components were met, but aspects of integrating its powertrain subsystems proved problematic. Electromagnetic interference (EMI) from the cruise motor controller (CMC) was a significant challenge for the project. This problem was exacerbated by the lack of EMI requirements imposed on subsystem powertrain components. This report presents the results of EMI testing of the X-57 high lift motor controller (HLMC) at the NASA Glenn Research Center’s EMI Laboratory. For reference, the conducted emissions are compared to DO–160G and MIL–STD–61G conducted emissions limits. After the EMI test, mitigation of the conducted emissions using lightweight EMI chokes produced at NASA Glenn was evaluated using the Fast Fourier Transform (FFT) capability of an oscilloscope in the hardware development laboratory. This process can contribute to the rapid prototyping of electric powertrain components and EMI filters and improve the likelihood of successful EMI qualification at the component and system levels.

Silicon carbide↗
DOE OSTI2021

Computational Fermi Level Engineering and Doping-Type Conversion of Ga2O3 Via Three-Step Processing

Ga2O3 is being actively explored for power electronics, deep-ultraviolet optoelectronics, and other applications due to its ultra-wide bandgap and low projected fabrication cost of large-size and high-quality crystals. N-type doping of Ga2O3 can be achieved and tuned, but p-type doping faces fundamental obstacles due to deep character of acceptor levels and polaron transport of resulting holes. However, successful engineering of Ga2O3 based devices requires critical control of doping density, Fermi level position, and free carrier concentration, providing opportunities for predictive process simulation. We use first-principles defect theory and defect equilibrium calculations to simulate a 3-step growth-annealing-quench protocol for hydrogen assisted Mg doping in Ga2O3, taking into account the hydrogen-oxygen-water gas phase equilibrium. We predict type conversion to a net p-type regime following O-rich annealing after growth under reducing conditions in the presence of H2. This process is similar to the Mg acceptor activation by H removal in GaN. We show that there is an optimal temperature that maximizes the net acceptor density during the equilibrium annealing step for a given Mg doping level. Quenching of non-equilibrium annealed samples then results in a Fermi level EF below mid-gap down to about EV +1.5 eV, creating a significant number of uncompensated neutral MgGa0 acceptors. The resulting free hole concentration in quenched samples is very low (109 – 1012 cm-3) due to deep energy level of these Mg acceptors, but this type converted Ga2O3 material can create a significant built-in field in a p-n junction with an adjoining n-type material. Additionally, the electron concentration is greatly suppressed in such acceptor-doped Ga2O3, which could enable the use as a current blocking layer to fabricate normally-off (enhancement-mode) vertical Ga2O3 based metal-oxide-semiconductor field effect transistors (MOSFETs), and as a guard ring for edge termination in MOSFETs and Schottky barrier diodes (SBDs) with increased breakdown voltage.

CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS,M↗
DOE OSTI2020

Multi-Scale Thermal Analysis for Design of SiC-Based Medium Voltage Motor Drive: Preprint

This paper describes a multi-scale thermal analysis approach for the design of an air-cooled 1.7-kV SiC MOSFET-based medium-voltage variable-speed motor drive. The National Renewable Energy Laboratory supported the project objectives by providing thermal management design support to the project partner The Ohio State University (OSU). The scope of the models and limited resources required efficient and flexible thermal models to be developed. Two modeling techniques are described that significantly reduced model run time and enabled more complex models to be run faster while retaining needed accuracy. The first technique uses the effectiveness-NTU method to extract convection boundary conditions from a computational fluid dynamics (CFD) model that can be applied to a fast-running finite element analysis model. The second is a porous media technique that enables system-level CFD simulations that incorporate effects from heat exchangers (e.g., pin fin heat sinks) that run in a fraction of the time required for fully resolved CFD simulations. The multi-scale approach to the thermal analysis enabled fast and accurate simulation for the converter design ranging from the die level up to the full system with 36 submodules. The modeling results were validated against experimental data from system tests performed by OSU.

DIRECT ENERGY CONVERSION↗