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NASA NTRS2010

Ultrasonic/Sonic Rotary-Hammer Drills

Ultrasonic/sonic rotary-hammer drill (USRoHD) is a recent addition to the collection of apparatuses based on ultrasonic/sonic drill corer (USDC). As described below, the USRoHD has several features, not present in a basic USDC, that increase efficiency and provide some redundancy against partial failure. USDCs and related apparatuses were conceived for boring into, and/or acquiring samples of, rock or other hard, brittle materials of geological interest. They have been described in numerous previous NASA Tech Briefs articles. To recapitulate: A USDC can be characterized as a lightweight, lowpower, piezoelectrically driven jackhammer in which ultrasonic and sonic vibrations are generated and coupled to a tool bit. A basic USDC includes a piezoelectric stack, an ultrasonic transducer horn connected to the stack, a free mass ( free in the sense that it can bounce axially a short distance between hard stops on the horn and the bit), and a tool bit. The piezoelectric stack creates ultrasonic vibrations that are mechanically amplified by the horn. The bouncing of the free mass between the hard stops generates the sonic vibrations. The combination of ultrasonic and sonic vibrations gives rise to a hammering action (and a resulting chiseling action at the tip of the tool bit) that is more effective for drilling than is the microhammering action of ultrasonic vibrations alone. The hammering and chiseling actions are so effective that unlike in conventional twist drilling, little applied axial force is needed to make the apparatus advance into the material of interest. There are numerous potential applications for USDCs and related apparatuses in geological exploration on Earth and on remote planets. In early USDC experiments, it was observed that accumulation of cuttings in a drilled hole causes the rate of penetration of the USDC to decrease steeply with depth, and that the rate of penetration can be increased by removing the cuttings. The USRoHD concept provides for removal of cuttings in the same manner as that of a twist drill: An USRoHD includes a USDC and a motor with gearhead (see figure). The USDC provides the bit hammering and the motor provides the bit rotation. Like a twist drill bit, the shank of the tool bit of the USRoHD is fluted. As in the operation of a twist drill, the rotation of the fluted drill bit removes cuttings from the drilled hole. The USRoHD tool bit is tipped with a replaceable crown having cutting teeth on its front surface. The teeth are shaped to promote fracturing of the rock face through a combination of hammering and rotation of the tool bit. Helical channels on the outer cylindrical surface of the crown serve as a continuation of the fluted surface of the shank, helping to remove cuttings. In the event of a failure of the USDC, the USRoHD can continue to operate with reduced efficiency as a twist drill. Similarly, in the event of a failure of the gearmotor, the USRoHD can continue to operate with reduced efficiency as a USDC.

Badescu, Mircea↗

NASA NTRS1974

Method and apparatus for decoding compatible convolutional codes

This invention relates to learning decoders for decoding compatible convolutional codes. The decoder decodes signals which have been encoded by a convolutional coder and allows performance near the theoretical limit of performance for coded data systems. The decoder includes a sub-bit shift register wherein the received sub-bits are entered after regeneration and shifted in synchronization with a clock signal recovered from the received sub-bit stream. The received sub-bits are processed by a sub-bit decision circuit, entered into a sub-bit shift register, decoded by a decision circuit, entered into a data shift register, and updated to reduce data errors. The bit decision circuit utilizes stored sub-bits and stored data bits to determine subsequent data-bits. Data errors are reduced by using at least one up-date circuit.

Doland, G. D.↗

NASA NTRS1980

Critique of a Hughes shuttle Ku-band data sampler/bit synchronizer

An alternative bit synchronizer proposed for shuttle was analyzed in a noise-free environment by considering the basic operation of the loop via timing diagrams and by linearizing the bit synchronizer as an equivalent, continuous, phased-lock loop (PLL). The loop is composed of a high-frequency phase-frequency detector which is capable of detecting both phase and frequency errors and is used to track the clock, and a bit transition detector which attempts to track the transitions of the data bits. It was determined that the basic approach was a good design which, with proper implementation of the accumulator, up/down counter and logic should provide accurate mid-bit sampling with symmetric bits. However, when bit asymmetry occurs, the bit synchronizer can lock up with a large timing error, yet be quasi-stable (timing will not change unless the clock and bit sequence drift). This will result in incorrectly detecting some bits.

Holmes, J. K.↗

NASA NTRS1990

Smart built-in test

The work which built-in test (BIT) is asked to perform in today's electronic systems increases with every insertion of new technology or introduction of tighter performance criteria. Yet the basic purpose remains unchanged -- to determine with high confidence the operational capability of that equipment. Achievement of this level of BIT performance requires the management and assimilation of a large amount of data, both realtime and historical. Smart BIT has taken advantage of advanced techniques from the field of artificial intelligence (AI) in order to meet these demands. The Smart BIT approach enhances traditional functional BIT by utilizing AI techniques to incorporate environmental stress data, temporal BIT information and maintenance data, and realtime BIT reports into an integrated test methodology for increased BIT effectiveness and confidence levels. Future research in this area will incorporate onboard fault-logging of BIT output, stress data and Smart BIT decision criteria in support of a singular, integrated and complete test and maintenance capability. The state of this research is described along with a discussion of directions for future development.

Richards, Dale W.↗

NASA NTRS2008

JPEG 2000 Encoding with Perceptual Distortion Control

An alternative approach has been devised for encoding image data in compliance with JPEG 2000, the most recent still-image data-compression standard of the Joint Photographic Experts Group. Heretofore, JPEG 2000 encoding has been implemented by several related schemes classified as rate-based distortion-minimization encoding. In each of these schemes, the end user specifies a desired bit rate and the encoding algorithm strives to attain that rate while minimizing a mean squared error (MSE). While rate-based distortion minimization is appropriate for transmitting data over a limited-bandwidth channel, it is not the best approach for applications in which the perceptual quality of reconstructed images is a major consideration. A better approach for such applications is the present alternative one, denoted perceptual distortion control, in which the encoding algorithm strives to compress data to the lowest bit rate that yields at least a specified level of perceptual image quality. Some additional background information on JPEG 2000 is prerequisite to a meaningful summary of JPEG encoding with perceptual distortion control. The JPEG 2000 encoding process includes two subprocesses known as tier-1 and tier-2 coding. In order to minimize the MSE for the desired bit rate, a rate-distortion- optimization subprocess is introduced between the tier-1 and tier-2 subprocesses. In tier-1 coding, each coding block is independently bit-plane coded from the most-significant-bit (MSB) plane to the least-significant-bit (LSB) plane, using three coding passes (except for the MSB plane, which is coded using only one "clean up" coding pass). For M bit planes, this subprocess involves a total number of (3M - 2) coding passes. An embedded bit stream is then generated for each coding block. Information on the reduction in distortion and the increase in the bit rate associated with each coding pass is collected. This information is then used in a rate-control procedure to determine the contribution of each coding block to the output compressed bit stream.

Watson, Andrew B.↗

NASA NTRS2011

Single Piezo-Actuator Rotary-Hammering Drill

This innovation comprises a compact drill that uses low-axial preload, via vibrations, that fractures the rock under the bit kerf, and rotates the bit to remove the powdered cuttings while augmenting the rock fracture via shear forces. The vibrations fluidize the powered cuttings inside the flutes around the bit, reducing the friction with the auger surface. These combined actions reduce the consumed power and the heating of the drilled medium, helping to preserve the pristine content of the produced samples. The drill consists of an actuator that simultaneously impacts and rotates the bit by applying force and torque via a single piezoelectric stack actuator without the need for a gearbox or lever mechanism. This reduces the development/fabrication cost and complexity. The piezoelectric actuator impacts the surface and generates shear forces, fragmenting the drilled medium directly under the bit kerf by exceeding the tensile and/or shear strength of the struck surface. The percussive impact action of the actuator leads to penetration of the medium by producing a zone of finely crushed rock directly underneath the struck location. This fracturing process is highly enhanced by the shear forces from the rotation and twisting action. To remove the formed cuttings, the bit is constructed with an auger on its internal or external surface. One of the problems with pure hammering is that, as the teeth become embedded in the sample, the drilling efficiency drops unless the teeth are moved away from the specific footprint location. By rotating the teeth, they are moved to areas that were not fragmented, and thus the rock fracturing is enhanced via shear forces. The shear motion creates ripping or chiseling action to produce larger fragments to increase the drilling efficiency, and to reduce the required power. The actuator of the drill consists of a piezoelectric stack that vibrates the horn. The stack is compressed by a bolt between the backing and the horn in order to prevent it from being subjected to tensile stress that will cause it to fail. The backing is intended to transfer the generated mechanical vibrations towards the horn. In order to cause rotation, the horn is configured asymmetrically with helical segments and, upon impacting the bit, it introduces longitudinal along the axis of the actuator and tangential force causing twisting action that rotates the bit. The longitudinal component of the vibrations of the stack introduces percussion impulses between the bit and the rock to fracture it when the ultimate strain is exceeded under the bit.

Sherrit, Stewart↗

NASA NTRS1982

The effects of transmitter/receiver clock time-base instability on coherent communication system performance

The purpose of this paper is to present a model and associated analysis of the deleterious effects which both transmitter and receiver data clock time-base instability have on bit-error probability. The types of time-base instability modeled and analyzed include what is commonly referred to as bit jitter (epoch jitter), bit-jitter rate (time interval jitter), and data asymmetry. The bit-error probability is determined as a function of the statistical characteristics of the time-base instability, the data-transition density, the signal-to-noise ratio in the bit-rate bandwidth and the mechanizations of both the data-bit detector and bit synchronizer. The latter is manifested through the bit synchronizer's natural frequency and loop-damping parameters. Numerical results which indicate the sensitivity of the system bit-error rate to various parameters of the model are provided.

Chie, C. M.↗

NASA NTRS2005

Reconfigurable data path processor

A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.

Donohoe, Gregory↗

NASA NTRS2007

Analog Nonvolatile Computer Memory Circuits

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

MacLeod, Todd↗

NASA NTRS1984

Optimum Cyclic Redundancy Codes for Noisier Channels

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16 bit American Data and Computer Communication Protocol (ADCCP) polynomial is designed for digital links which already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of resulting digital circuit may be much lower. The 3 byte (24 bit) and 4 byte (32 bit) polynomials are considered. Generator polynomials of a certain class have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular choices for 24 bit and 32 bit redundancies are exhibited: of weight and distance 6 in the 24-bit case; and weight 10 and distance 8 in the 32-bit case.

Merkey, P.↗

NASA NTRS1984

Optimum cyclic redundancy codes for noisy channels

Merkey, P.↗

NASA NTRS1996

DCTune Perceptual Optimization of Compressed Dental X-Rays

In current dental practice, x-rays of completed dental work are often sent to the insurer for verification. It is faster and cheaper to transmit instead digital scans of the x-rays. Further economies result if the images are sent in compressed form. DCTune is a technology for optimizing DCT (digital communication technology) quantization matrices to yield maximum perceptual quality for a given bit-rate, or minimum bit-rate for a given perceptual quality. Perceptual optimization of DCT color quantization matrices. In addition, the technology provides a means of setting the perceptual quality of compressed imagery in a systematic way. The purpose of this research was, with respect to dental x-rays, 1) to verify the advantage of DCTune over standard JPEG (Joint Photographic Experts Group), 2) to verify the quality control feature of DCTune, and 3) to discover regularities in the optimized matrices of a set of images. We optimized matrices for a total of 20 images at two resolutions (150 and 300 dpi) and four bit-rates (0.25, 0.5, 0.75, 1.0 bits/pixel), and examined structural regularities in the resulting matrices. We also conducted psychophysical studies (1) to discover the DCTune quality level at which the images became 'visually lossless,' and (2) to rate the relative quality of DCTune and standard JPEG images at various bitrates. Results include: (1) At both resolutions, DCTune quality is a linear function of bit-rate. (2) DCTune quantization matrices for all images at all bitrates and resolutions are modeled well by an inverse Gaussian, with parameters of amplitude and width. (3) As bit-rate is varied, optimal values of both amplitude and width covary in an approximately linear fashion. (4) Both amplitude and width vary in systematic and orderly fashion with either bit-rate or DCTune quality; simple mathematical functions serve to describe these relationships. (5) In going from 150 to 300 dpi, amplitude parameters are substantially lower and widths larger at corresponding bit-rates or qualities. (6) Visually lossless compression occurs at a DCTune quality value of about 1. (7) At 0.25 bits/pixel, comparative ratings give DCTune a substantial advantage over standard JPEG. As visually lossless bit-rates are approached, this advantage of necessity diminishes. We have concluded that DCTune optimized quantization matrices provide better visual quality than standard JPEG. Meaningful quality levels may be specified by means of the DCTune metric. Optimized matrices are very similar across the class of dental x-rays, suggesting the possibility of a 'class-optimal' matrix. DCTune technology appears to provide some value in the context of compressed dental x-rays.

Watson, Andrew B.↗

NASA NTRS2010

Performance Bounds on Two Concatenated, Interleaved Codes

A method has been developed of computing bounds on the performance of a code comprised of two linear binary codes generated by two encoders serially concatenated through an interleaver. Originally intended for use in evaluating the performances of some codes proposed for deep-space communication links, the method can also be used in evaluating the performances of short-block-length codes in other applications. The method applies, more specifically, to a communication system in which following processes take place: At the transmitter, the original binary information that one seeks to transmit is first processed by an encoder into an outer code (Co) characterized by, among other things, a pair of numbers (n,k), where n (n > k)is the total number of code bits associated with k information bits and n k bits are used for correcting or at least detecting errors. Next, the outer code is processed through either a block or a convolutional interleaver. In the block interleaver, the words of the outer code are processed in blocks of I words. In the convolutional interleaver, the interleaving operation is performed bit-wise in N rows with delays that are multiples of B bits. The output of the interleaver is processed through a second encoder to obtain an inner code (Ci) characterized by (ni,ki). The output of the inner code is transmitted over an additive-white-Gaussian- noise channel characterized by a symbol signal-to-noise ratio (SNR) Es/No and a bit SNR Eb/No. At the receiver, an inner decoder generates estimates of bits. Depending on whether a block or a convolutional interleaver is used at the transmitter, the sequence of estimated bits is processed through a block or a convolutional de-interleaver, respectively, to obtain estimates of code words. Then the estimates of the code words are processed through an outer decoder, which generates estimates of the original information along with flags indicating which estimates are presumed to be correct and which are found to be erroneous. From the perspective of the present method, the topic of major interest is the performance of the communication system as quantified in the word-error rate and the undetected-error rate as functions of the SNRs and the total latency of the interleaver and inner code. The method is embodied in equations that describe bounds on these functions. Throughout the derivation of the equations that embody the method, it is assumed that the decoder for the outer code corrects any error pattern of t or fewer errors, detects any error pattern of s or fewer errors, may detect some error patterns of more than s errors, and does not correct any patterns of more than t errors. Because a mathematically complete description of the equations that embody the method and of the derivation of the equations would greatly exceed the space available for this article, it must suffice to summarize by reporting that the derivation includes consideration of several complex issues, including relationships between latency and memory requirements for block and convolutional codes, burst error statistics, enumeration of error-event intersections, and effects of different interleaving depths. In a demonstration, the method was used to calculate bounds on the performances of several communication systems, each based on serial concatenation of a (63,56) expurgated Hamming code with a convolutional inner code through a convolutional interleaver. The bounds calculated by use of the method were compared with results of numerical simulations of performances of the systems to show the regions where the bounds are tight (see figure).

Moision, Bruce↗

NASA NTRS2006

Active Struts With Variable Spring Stiffness and Damping

An ultrasonic rock-abrasion tool (URAT) was developed using the same principle of ultrasonic/sonic actuation as that of the tools described in two prior NASA Tech Briefs articles: Ultrasonic/ Sonic Drill/Corers With Integrated Sensors (NPO-20856), Vol. 25, No. 1 (January 2001), page 38 and Ultrasonic/ Sonic Mechanisms for Drilling and Coring (NPO-30291), Vol. 27, No. 9 (September 2003), page 65. Hence, like those tools, the URAT offers the same advantages of low power demand, mechanical simplicity, compactness, and ability to function with very small axial loading (very small contact force between tool and rock). Like a tool described in the second of the cited previous articles, a URAT includes (1) a drive mechanism that comprises a piezoelectric ultrasonic actuator, an amplification horn, and a mass that is free to move axially over a limited range and (2) an abrasion tool bit. A URAT tool bit is a disk that has been machined or otherwise formed to have a large number of teeth and an overall shape chosen to impart the desired shape (which could be flat or curved) to the rock surface to be abraded. In operation, the disk and thus the teeth are vibrated in contact with the rock surface. The concentrated stresses at the tips of the impinging teeth repeatedly induce microfractures and thereby abrade the rock. The motion of the tool induces an ultrasonic transport effect that displaces the cuttings from the abraded area. The figure shows a prototype URAT. A piezoelectric-stack/horn actuator is housed in a cylindrical container. The movement of the actuator and bit with respect to the housing is aided by use of mechanical sliders. A set of springs accommodates the motion of the actuator and bit into or out of the housing through an axial range between 5 and 7 mm. The springs impose an approximately constant force of contact between the tool bit and the rock to be abraded. A dust shield surrounds the bit, serving as a barrier to reduce the migration of rock debris to sensitive instrumentation or mechanisms in the vicinity. A bushing at the tool-bit end of the housing reduces the flow of dust into the actuator and retains the bit when no axial load is applied.

Farley, Gary L.↗

NASA NTRS2006

Ultrasonically Actuated Tools for Abrading Rock Surfaces

Dolgin, Benjamin↗

NASA NTRS2004

Ultralow-Power Digital Correlator for Microwave Polarimetry

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

Piepmeier, Jeffrey R.↗

NASA NTRS1977

Bandwidth compression of synthetic aperture radar imagery by quantization of raw radar data

A study is made of the effects of quantization of the radar returns transmitted from aircraft or spacecraft employing a synthetic aperture radar system. The study is based on the output images obtained after one-bit, two-bit, and eight-bit quantizations and comparing the results to ground truth. In this way the degradation resulting from data or bandwidth reduction is determined. Quantization is evaluated in terms of crater scene, number of looks, and transmission error rate. It is found that two-bit quantization of raw radar data from homogeneous scenes processed to 32 looks yields nearly all the details of the original. One-bit quantization of raw radar data from homogeneous scenes processed to 32 looks yields a good visual representation of the scene but some fine detail is lost and the absolute reflectivity level is not reliable. Image quality is observed to improve with more looks and video and intermediate frequency quantization are not distinguishable even for one-bit quantizations. Image quality is not influenced by bit error rates less than about 2 to the -7th power.

Lipes, R. G.↗

NASA NTRS1981

The effects of transmitter/receiver clock time base instability on coherent communication system performance

The purpose of this paper is to present a model and associated analysis of the deleterious effects which both transmitter and receiver data clock time-base instability have on bit error probability. The types of time-base instability modeled and analyzed include bit jitter (epoch jitter), bit jitter rate (time interval jitter) and data asymmetry. The bit error probability is determined as a function of the statistical characteristics of the time-base instability, the data transition density, the signal-to-noise ratio in the bit rate bandwidth and the mechanizations of both the data bit detector and bit synchronizer. Numerical results are provided.

Chie, C. M.↗