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Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.
Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.
Integrated optic waveguide circuits with a phase bias and modulator on the same chip were designed, fabricated, and tested for use in a fiber-optic rotation sensor (gyro) under development. Single mode fiber-optic pigtails were permanently coupled to the four ports of the chip. The switch format was based on coherent coupling between waveguides formed in Z-cut LiNbO3. The control of the coupling was achieved by electro-optically varying the phase propagation constants of each guide. Fiber-to-chip interfacing required the development of appropriate fixturing and manipulation techniques to achieve the close tolerance needed for high coupling efficiency between a fiber with an approximately 5 micron m core and a channel guide with a roughly 2 micron m by 5 micron m cross section. Switch and chip performance at 0.85 micron m is discussed as well as potential improvements related to insertion loss reduction, switching voltages, and suppression of Li2O out-diffusion.
Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.
A NASA-wide team, funded under the NASA Electronic Parts and Packaging Program (NEPP), was formed to collaborate and to establish reliability of various electronic parts/packaging and assemblies for operation under extreme cold temperatures. One of the primary objectives of the NEPP is to expedite the infusion of cutting edge technologies into the present and future NASA missions. Commercial-off-the-shelf (COTS) emerging electronic parts/packages due to their lower weight, increased functionality, and lower cost are excellent candidates for space missions if they are characterized to show that they will meet the stringent reliability and quality requirements. Characterizations, especially for the extreme cold temperatures, are required since very limited data are available by manufacturers or users. For severe military environments, the temperature conditions to -65 C are the lowest temperature for which these parts/packages and assemblies are qualified. New data beyond this relatively benign cold temperature are required for numerous NASA missions. Several parts/packages, based on the project recommendation for their immediate and future needs, were selected for detailed characterization to cold temperature regimes down to liquid nitrogen (-196 C), covering both Mars cold temperature (-125 C) and asteroid (- 180 C) lander environmental requirements. Numerous parts/packages and assemblies were characterized during extreme temperature environmental tests. Several electrical parameters were characterized at discrete temperatures to -185 C to determine if they remain within their specification ranges. Both packages and circuit boards were subjected to nondestructive testing including optical, X-ray, and acoustic microscopy to document their integrity prior to environment exposure. Package/board assemblies were also subjected to X-ray to characterize solder joint integrity including void levels. Both parts and assemblies were subjected to thermal cycling with a large temperature swing enveloping numerous NASA missions. Details of the performed tests and the results obtained are presented.
Space radiation damage and proton induced transient effects were evaluated on 4.4 μm cutoff HgCdTe avalanche photodiode (APD) arrays developed by Leonardo DRS. Device performances as a function of total dose up to 100 krad (Si) were measured with ~60 MeV protons on 3 types of APD samples: 4x4 pixel APD fanout arrays with and without connection to a read-out integrated circuit (ROIC), and a 2x8 pixel photon counting APD focal plane array (FPA). A gamma-ray test was also conducted to study ionization effects. Both APD arrays exhibited a small decrease in the quantum efficiency and a linear increase in the dark current with the proton fluence. The 2x8 pixel photon counting FPA also exhibited an increase in the dark count rate with proton dose. After the proton irradiation and an overnight room temperature warm-up, the APD dark currents at 80 K increased significantly in both types of APD arrays. All radiation damage to these HgCdTe APD arrays annealed out after baking them at >85 °C for several hours. Transient protons through the devices were found to cause large pulses at the detector output but recover within 1 μs.
The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.
The key to implementing self-diagnosing design is a systems engineering task focused on design for testability concurrent with design for functionality. The design for testability process described here is the product of several years of DOD study and experience. Its application to the space station has begun on Work Package II under NASA and McDonnell direction. Other work package teams are being briefed by Harris Corporation with the hope of convincing them to embrace the process. For the purpose of this discussion the term testability is used to describe the systems engineering process by which designers can assure themselves and their reviewers that their designs are TESTABLE, that is they will support the downstream process of determining their functionality. Due to the complexity and density of present-day state-of-the-art designs, such as pipeline processors and high-speed integrated circuit technology, testability feature design is a critical requirement of the functional design process. A systematic approach to Space systems test and checkout as well as fault detection fault isolation reconfiguration (FDFIR) will minimize operational costs and maximize operational efficiency. An effective design for the testability program must be implemented by all contractors to insure meeting this objective. The process is well understood and technology is here to support it.
We have developed a range of techniques useful for constructing analog and digital circuits for operation in a liquid Helium environment (4.2K), using commercially available low power components. The challenges encountered in designing cryogenic electronics include finding components that can function usefully in the cold and possess low enough power dissipation so as not to heat the systems they are designed to measure. From design, test, and integration perspectives it is useful for components to operate similarly at room and cryogenic temperatures; however this is not a necessity. Some of the circuits presented here have been used successfully in the MUSTANG and in the GISMO camera to build a complete digital to analog multiplexer (which will be referred to as the Cryogenic Address Driver board). Many of the circuit elements described are of a more general nature rather than specific to the Cryogenic Address Driver board, and were studied as a part of a more comprehensive approach to addressing a larger set of cryogenic electronic needs.
A CMOS Process Monitor, consisting of eight basic test structures, has been prepared to acquire key CMOS parameters to assist in VLSI wafer acceptance. The test structures can be probed using a 2 by N probe pad array and can be arranged to fit into either the interior or the scribe lane of an integrated circuit chip. In order to facilitate the general use of the monitor, a document is being prepared that describes its design, layout, measurement, and analysis. This paper describes the structures included in the monitor, the methodology used to create the monitor, and test results from the monitor.
Experimentally, thermal annealing is known to be a factor which enables a number of different integrated circuits (IC's) to recover their operating characteristics after suffering radiation damage in the space radiation environment; thus, decreasing and limiting long term cumulative total-dose effects. This annealing is also known to be accelerated at elevated temperatures both during and after irradiation. Linear response theory (LRT) was applied, and a linear response function (LRF) to predict the radiation/annealing response of sensitive parameters of IC's for long term (several months or years) exposure to the space radiation environment were constructed. Compressing the annealing process from several years in orbit to just a few hours or days in the laboratory is achieved by subjecting the IC to elevated temperatures or by increasing the typical spaceflight dose rate by several orders of magnitude for simultaneous radiation/annealing only. The accomplishments are as follows: (1) the test procedure to make predictions of the radiation response was developed; (2) the calculation of the shift in the threshold potential due to the charge distribution in the oxide was written; (3) electron tunneling processes from the bulk Si to the oxide region in an MOS IC were estimated; (4) in order to connect the experimental annealing data to the theoretical model, constants of the model of the basic annealing process were established; (5) experimental data obtained at elevated temperatures were analyzed; (6) time compression and reliability of predictions for the long term region were shown; (7) a method to compress test time and to make predictions of response for the nonlinear region was proposed; and (8) nonlinearity of the LRF with respect to log(t) was calculated theoretically from a model.
An automatic gain control (AGC), designed to operate with the prototype Loran-C receiver, is described. The device is used to eliminate error which occurs when signals are received at different magnitudes. The automatic gain control is a three transistor circuit which requires a constant dc voltage of 8 volts. Tests conclude that this value may be in the range of 4 to 12 v without change in circuit performance. Two transistors are cascaded to pass and amplify the input signal. Their gain is controlled by a third transistor which itself is controlled by an external AGC voltage between 0 and 8 volts dc. The integrated circuit used is an 8 pin chip, which is a differential cascade amplifier designed for use in communications operating at frequencies from dc to 120 MHz. The integrated circuit was balanced for AGC capabilities, and has a wide operating current range. The maximum input current at pins 1 and 5 is 0.1 mAmps. AGC testing is described.
Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.
NASA contributions to the advancement of major developments in twelve selected fields of technology are presented. The twelve fields of technology discussed are: (1) cryogenics, (2) electrochemical energy conversion and storage, (3) high-temperature ceramics, (4) high-temperature metals (5) integrated circuits, (6) internal gas dynamics (7) materials machining and forming, (8) materials joining, (9) microwave systems, (10) nondestructive testing, (11) simulation, and (12) telemetry. These field were selected on the basis of both NASA and nonaerospace interest and activity.
Algorithms yield feedback shift registers with maximum regularity. Report provides extensive mathematical treatment of new and previous results related to generation of pseudo-noise binary sequences by feedback shift registers. Generator architectures amenable to efficient implementation in very-large-scale integrated (VLSI) circuits. Report includes literature references to applications of such sequences in random-number generation, radar, VLSI testing, data encryption and decryption, algebraic error-detection and error-correction encoding and decoding, and feedback-shift-register synthesis of sequential machines.
Programmable maintenance processor (MAINT) made of commercially available integrated circuits. Autonomous one of four digital electronic processors in extended aircraft interrogation and display system (XAIDS). Developed for testing of system and application computer programs as well as for testing equipment. MAINT has independent terminal and printer interfaces and dedicated magnetic bubble memory storing system-testing sequences entered from terminal. Software for MAINT written in PLM86 programming language and broken into four separate modules.
Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.
We report the results from proton and gamma ray radiation testing of HgCdTe avalanche photodiode (APD) arrays developed by Leonardo DRS for space lidar detectors. We tested these devices with both approximately 60 MeV protons and gamma rays, with and without the read out integrated circuit (ROIC). We also measured the transient responses with the device fully powered and with the APD gain from unity to greater than 1000. The detectors produced a large current impulse in response to each proton hit but the response completely recovered within 1 microsecond. The devices started to have persistent damage at a proton fluence of 7e10 protons/cm2, equivalent to 10 krad(Si) total ionization dose. The dark current became much higher after the device was warmed to room temperature and cooled to 80K again, but it completely annealed after baking at 85 C for several hours. These results showed the HgCdTe APD arrays are suitable for use in space lidar for typical Earth orbiting and planetary missions provided that provisions are made to heat the detector chip to 85 C for several hours after radiation damage becomes evident that system performance is impacted.