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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19

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NASA NTRS1976

Convolutional code performance in the Rician fading channel

The performance of short constraint length convolutional codes in conjunction with binary phase-shift keyed (BPSK) modulation and Viterbi maximum likelihood decoding on the classical Rician fading channel is examined in detail. Primary interest is in the bit error probability performance as a function of E sub b/N sub 0 parameterized by the fading channel parameters. Fairly general upper bounds on bit error probability performance in the presence of fading are obtained and compared with simulation results in the two extremes of zero channel memory and infinite channel memory. The efficacy of simple block interleaving in combating the memory of the channel is thoroughly explored. Results include the effects of fading on tracking loop performance and the subsequent impact on overall coded system performance. The approach is analytical where possible; otherwise resort is made to digital computer simulation.

Modestino, J. W.↗

NASA NTRS1996

Load Balancing Unstructured Adaptive Grids for CFD Problems

Mesh adaption is a powerful tool for efficient unstructured-grid computations but causes load imbalance among processors on a parallel machine. A dynamic load balancing method is presented that balances the workload across all processors with a global view. After each parallel tetrahedral mesh adaption, the method first determines if the new mesh is sufficiently unbalanced to warrant a repartitioning. If so, the adapted mesh is repartitioned, with new partitions assigned to processors so that the redistribution cost is minimized. The new partitions are accepted only if the remapping cost is compensated by the improved load balance. Results indicate that this strategy is effective for large-scale scientific computations on distributed-memory multiprocessors.

Biswas, Rupak↗

NASA NTRS1989

Psychology of computer use: IX. A menu of self-administered microcomputer-based neurotoxicology tests

This study examined the feasibility of repeated self-administration of a newly developed battery of mental acuity tests which may have application in screening for fitness-for-duty or for persons who may be exposed to environmental stress, toxic agents, or disease. 16 subjects self-administered 18 microcomputer-based tests (13 new, 5 "core"), without proctors, over 10 sessions. The hardware performed well throughout the study and the tests appeared to be easily self-administered. Stabilities and reliabilities of the tests from the "core" battery were comparable to those obtained previously under more controlled experimental conditions. Eight of the new tests exceeded minimum criteria for metric and practical requirements and can be recommended as additions to the menu. Although the average retest reliability was high, cross-correlations between tests were low, implying factorial diversity. The menu can be used to form batteries with flexible total testing time which are likely to tap different mental processes and functions.

NASA Discipline Neuroscience↗

NASA NTRS2008

Model-based fault detection and isolation for intermittently active faults with application to motion-based thruster fault detection and isolation for spacecraft

The present invention is a method for detecting and isolating fault modes in a system having a model describing its behavior and regularly sampled measurements. The models are used to calculate past and present deviations from measurements that would result with no faults present, as well as with one or more potential fault modes present. Algorithms that calculate and store these deviations, along with memory of when said faults, if present, would have an effect on the said actual measurements, are used to detect when a fault is present. Related algorithms are used to exonerate false fault modes and finally to isolate the true fault mode. This invention is presented with application to detection and isolation of thruster faults for a thruster-controlled spacecraft. As a supporting aspect of the invention, a novel, effective, and efficient filtering method for estimating the derivative of a noisy signal is presented.

Wilson, Edward↗

NASA NTRSDate not supplied

Scalability of GlennICE in a Parallel Environment

GlennICE (Glenn Icing Computational Environment) is a comptational tool designed to calculate ice growth on complex three- dimensional geometries using the input from a user-supplied computational fluid dynamics (CFD) solution for the geometry of interest. The most significant developments in the advancement of GlennICE have been investigating the convergence of the collection efficiency, efficiently finding trajectories, and improving the refinement methodology. Such developments have increased the efficiency of GlennICE for tractability in a practical engineering application. Although studies have demonstrated a reduction in the amount of work (memory footprint) required, research has yet to systematically investigate the effects of scaling GlennICE. This paper sets out to benchmark the scalability of GlennICE within a parallel environment and investigate if an increase in the number of processors result in a linear speed up.

Computational Icing↗

NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗

NASA NTRSDate not supplied

Neurobehavioral Effects Of Five-Ion GCRSim Exposure In Male And Female Mice

Exposure to space galactic cosmic radiation is a principal consideration of spaceflight missions, and with upcoming missions to the Moon and Mars, it is increasingly imperative to elucidate the detrimental effects of space travel beyond the lower Earth orbit. Additionally, with the first female astronaut to soon travel to the Moon and beyond lower Earth orbit, there is a strong need to understand the biological sex differences to adaptation to the deep space environment. While the effects of spaceflight on the nervous system are not fully known, studies in animal models have shown that exposure to ionizing radiation can cause neuronal damage and lead to downstream cognitive and behavioral deficits. Therefore, we investigated the neurobehavioral responses to space environment-like radiation exposure. Male and female 23–24-week-old mice (age-matched to average astronaut age) were exposed to 5, 15 and 50 cGy via Five-Ion Galactic Cosmic Ray Simulation at the NASA National Space Radiation Laboratory at Brookhaven National Laboratory. Both early (72hrs post exposure) and late (1-4 months post exposure) cognitive and behavioral deficits were investigated. In-cage behavior was analyzed as frequency/duration of digging, rearing, and grooming and nestlet building using a 5-stage Deacon score. Additionally, at NASA Ames, behavior tests included Catwalk (gait), Zero Maze (anxiety), Adhesive Removal (sensory motor), Novel Object Recognition and Barnes Maze (working memory). There were pronounced sex differences in both early and late time points. Females typically performed the tests better than males, specifically in nestlet building, gait and working memory, though males performed better at the sensory motor (adhesive removal) test. Dose effects were primarily observed at 50 cGy for both sexes, particularly with the Barnes Maze (working memory), where both males and females exposed to 50 cGy showed little to no improvement in test performance, though females again performed better than males. Currently, we are investigating the correlations between the observed behavior and cytokine levels in the plasma and brain. Future studies will continue to investigate cognitive consequences of galactic cosmic radiation in combination with other space-like environment stressors, including antigravity and social versus single housing.

Stephanie Puukila↗

NASA NTRSDate not supplied

Neurobehavioral Effects Of Five-Ion GCRSim Exposure In Male And Female Mice

S. Puukila↗

NASA NTRS1992

Scalable parallel communications

Coarse-grain parallelism in networking (that is, the use of multiple protocol processors running replicated software sending over several physical channels) can be used to provide gigabit communications for a single application. Since parallel network performance is highly dependent on real issues such as hardware properties (e.g., memory speeds and cache hit rates), operating system overhead (e.g., interrupt handling), and protocol performance (e.g., effect of timeouts), we have performed detailed simulations studies of both a bus-based multiprocessor workstation node (based on the Sun Galaxy MP multiprocessor) and a distributed-memory parallel computer node (based on the Touchstone DELTA) to evaluate the behavior of coarse-grain parallelism. Our results indicate: (1) coarse-grain parallelism can deliver multiple 100 Mbps with currently available hardware platforms and existing networking protocols (such as Transmission Control Protocol/Internet Protocol (TCP/IP) and parallel Fiber Distributed Data Interface (FDDI) rings); (2) scale-up is near linear in n, the number of protocol processors, and channels (for small n and up to a few hundred Mbps); and (3) since these results are based on existing hardware without specialized devices (except perhaps for some simple modifications of the FDDI boards), this is a low cost solution to providing multiple 100 Mbps on current machines. In addition, from both the performance analysis and the properties of these architectures, we conclude: (1) multiple processors providing identical services and the use of space division multiplexing for the physical channels can provide better reliability than monolithic approaches (it also provides graceful degradation and low-cost load balancing); (2) coarse-grain parallelism supports running several transport protocols in parallel to provide different types of service (for example, one TCP handles small messages for many users, other TCP's running in parallel provide high bandwidth service to a single application); and (3) coarse grain parallelism will be able to incorporate many future improvements from related work (e.g., reduced data movement, fast TCP, fine-grain parallelism) also with near linear speed-ups.

Maly, K.↗

NASA NTRS2003

Micro-Ball-Lens Optical Switch Driven by SMA Actuator

The figure is a simplified cross section of a microscopic optical switch that was partially developed at the time of reporting the information for this article. In a fully developed version, light would be coupled from an input optical fiber to one of two side-by-side output optical fibers. The optical connection between the input and the selected output fiber would be made via a microscopic ball lens. Switching of the optical connection from one output fiber to another would be effected by using a pair of thin-film shape-memory-alloy (SMA) actuators to toggle the lens between two resting switch positions. There are many optical switches some made of macroscopic parts by conventional fabrication techniques and some that are microfabricated and, hence, belong to the class of microelectromechanical systems (MEMS). Conventionally fabricated optical switches tend to be expensive. MEMS switches can be mass-produced at relatively low cost, but their attractiveness has been diminished by the fact that, heretofore, MEMS switches have usually been found to exhibit high insertion losses. The present switch is intended to serve as a prototype of low-loss MEMS switches. In addition, this is the first reported SMA-based optical switch. The optical fibers would be held in V grooves in a silicon frame. The lens would have a diameter of 1 m; it would be held by, and positioned between, the SMA actuators, which would be made of thin films of TiNi alloy. Although the SMA actuators are depicted here as having simple shapes for the sake of clarity of illustration, the real actuators would have complex, partly net-like shapes. With the exception of the lens and the optical fibers, the SMA actuators and other components of the switch would be made by microfabrication techniques. The components would be assembled into a sandwich structure to complete the fabrication of the switch. To effect switching, an electric current would be passed through one of the SMA actuators to heat it above its transition temperature, thereby causing it to deform to a different "remembered" shape. The two SMA actuators would be stiff enough that once switching had taken place and the electrical current was turned off, the lens would remain latched in the most recently selected position. In a test, the partially developed switch exhibited an insertion loss of only -1.9 dB and a switching contrast of 70 dB. One the basis of prior research on SMA actuators and assuming a lens displacement of 125 m between extreme positions, it has been estimated that the fully developed switch would be capable of operating at a frequency as high as 10 Hz.

Yang, Eui-Hyeok↗

NASA NTRS1993

Mapping robust parallel multigrid algorithms to scalable memory architectures

The convergence rate of standard multigrid algorithms degenerates on problems with stretched grids or anisotropic operators. The usual cure for this is the use of line or plane relaxation. However, multigrid algorithms based on line and plane relaxation have limited and awkward parallelism and are quite difficult to map effectively to highly parallel architectures. Newer multigrid algorithms that overcome anisotropy through the use of multiple coarse grids rather than line relaxation are better suited to massively parallel architectures because they require only simple point-relaxation smoothers. The parallel implementation of a V-cycle multiple semi-coarsened grid (MSG) algorithm or distributed-memory architectures such as the Intel iPSC/860 and Paragon computers is addressed. The MSG algorithms provide two levels of parallelism: parallelism within the relaxation or interpolation on each grid and across the grids on each multigrid level. Both levels of parallelism must be exploited to map these algorithms effectively to parallel architectures. A mapping of an MSG algorithm to distributed-memory architectures that demonstrate how both levels of parallelism can be exploited is described. The results is a robust and effective multigrid algorithm for distributed-memory machines.

Overman, Andrea↗

NASA NTRS1984

Impact of computers on aerodynamics research and development

Factors motivating the development of computational aerodynamics as a discipline are traced back to the limitations of the tools available to the aerodynamicist before the development of digital computers. Governing equations in exact and approximate forms are discussed together with approaches to their numerical solution. Example results obtained from the successively refined forms of the equations are presented and discussed, both in the context of levels of computer power required and the degree of the effect that their solution has on aerodynamic research and development. Factors pacing advances in computational aerodynamics are identified, including the amount of computational power required to take the next major step in the discipline. Finally, the Numerical Aerodynamic Simulation (NAS) Program - with its 1987 target of achieving a sustained computational rate of 1 billion floating-point operations per second operating on a memory of 240 million words - is briefly discussed in terms of its projected effect on the future of computational aerodynamics.

Peterson, V. L.↗

NASA NTRS1981

The persistence of a visual dominance effect in a telemanipulator task: A comparison between visual and electrotactile feedback

The possibility to use an electrotactile stimulation in teleoperation and to observe the interpretation of such information as a feedback to the operator was investigated. It is proposed that visual feedback is more informative than an electrotactile one; and that complex electrotactile feedback slows down both the motor decision and motor response processes, is processed as an all or nothing signal, and bypasses the receptive structure and accesses directly in a working memory where information is sequentially processed and where memory is limited in treatment capacity. The electrotactile stimulation is used as an alerting signal. It is suggested that the visual dominance effect is the result of the advantage of both a transfer function and a sensory memory register where information is pretreated and memorized for a short time. It is found that dividing attention has an effect on the acquisition of the information but not on the subsequent decision processes.

Gaillard, J. P.↗

NASA NTRS1987

Implementation of a digital optical matrix-vector multiplier using a holographic look-up table and residue arithmetic

The design and implementation of a digital (numerical) optical matrix-vector multiplier are presented. The objective is to demonstrate the operation of an optical processor designed to minimize computation time in performing a practical computing application. This is done by using the large array of processing elements in a Hughes liquid crystal light valve, and relying on the residue arithmetic representation, a holographic optical memory, and position coded optical look-up tables. In the design, all operations are performed in effectively one light valve response time regardless of matrix size. The features of the design allowing fast computation include the residue arithmetic representation, the mapping approach to computation, and the holographic memory. In addition, other features of the work include a practical light valve configuration for efficient polarization control, a model for recording multiple exposures in silver halides with equal reconstruction efficiency, and using light from an optical fiber for a reference beam source in constructing the hologram. The design can be extended to implement larger matrix arrays without increasing computation time.

Habiby, Sarry F.↗

NASA NTRS1981

Transient upsets in microprocessor controllers

The modeling and analysis of transient faults in microprocessor based controllers are discussed. Such controllers typically consist of a microprocessor, read only memory storing and application program, random access memory for data storage, and input/output devices for external communications. The effects of transient faults on the performance of the controller are reviewed. An instruction level perspective of performance is taken which is the basis of a useful high level program state description of the microprocessor controller. A transition matrix is defined which determines the controller's response to transient fault arrivals.

Glaser, R. E.↗

NASA NTRS1987

Equations For Fading-Memory Filters

Report discusses simplified recursive solutions for equations of class of fading-memory filters. Under appropriate assumptions regarding noise and exponential decay of effects of previous states, filter equations reduced to analytic formulas in closed form.

Statman, J. I.↗

NASA NTRS1988

A sparse matrix algorithm on the Boolean vector machine

VLSI technology is being used to implement a prototype Boolean Vector Machine (BVM), which is a large network of very small processors with equally small memories that operate in SIMD mode; these use bit-serial arithmetic, and communicate via cube-connected cycles network. The BVM's bit-serial arithmetic and the small memories of individual processors are noted to compromise the system's effectiveness in large numerical problem applications. Attention is presently given to the implementation of a basic matrix-vector iteration algorithm for space matrices of the BVM, in order to generate over 1 billion useful floating-point operations/sec for this iteration algorithm. The algorithm is expressed in a novel language designated 'BVM'.

Wagner, Robert A.↗

NASA NTRS1991

A Parallel Rendering Algorithm for MIMD Architectures

Applications such as animation and scientific visualization demand high performance rendering of complex three dimensional scenes. To deliver the necessary rendering rates, highly parallel hardware architectures are required. The challenge is then to design algorithms and software which effectively use the hardware parallelism. A rendering algorithm targeted to distributed memory MIMD architectures is described. For maximum performance, the algorithm exploits both object-level and pixel-level parallelism. The behavior of the algorithm is examined both analytically and experimentally. Its performance for large numbers of processors is found to be limited primarily by communication overheads. An experimental implementation for the Intel iPSC/860 shows increasing performance from 1 to 128 processors across a wide range of scene complexities. It is shown that minimal modifications to the algorithm will adapt it for use on shared memory architectures as well.

Crockett, Thomas W.↗