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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
NASA NTRS1980

TIROS-N Cosmic Ray study

An experimental and analytical study was performed on the impact of galactic cosmic rays on the TIROS-N satellite memory in orbit. Comparisons were made of systems equipped with the Harris HMI-6508 1 x 1024 CMOS/bulk RAM and the RCA CDP-1821 1 x 1024 bit CMOS/SOS RAM. Based upon the experimental results, estimated bit error rates were determined. These were at least 8.0 bit errors/day for a 300 kilobit memory with the HMI-6508 and .014 bit errors/day with the CDF-1821. It was also estimated that the HMI-6508 latchup rate in orbit is at least two orders of magnitude less than the bit error rates; the CDP-1821 will not latchup.

Blandford, J. T., Jr.↗
NASA NTRS1986

Fast VLSI Viterbi Decoder

Fast Viterbi decoder with fully parallel, pipeline architecture implemented on two VLSI NMOS chips. Decoder used with constraint-length-7, rate-1/2, convolutional error-correcting code widely used by NASA for deepspace telemetry data. With this (7,1/2) code, bit stream contains 2 bits per original data bit, and information about 1 data bit distributed over 7 pairs of bits. Design principles of decoder also applicable to Viterbi codes of other lengths and rates.

Wang, C. C.↗
NASA NTRS1984

The Single Event Upset (SEU) response to 590 MeV protons

The presence of high-energy protons in cosmic rays, solar flares, and trapped radiation belts around Jupiter poses a threat to the Galileo project. Results of a test of 10 device types (including 1K RAM, 4-bit microP sequencer, 4-bit slice, 9-bit data register, 4-bit shift register, octal flip-flop, and 4-bit counter) exposed to 590 MeV protons at the Swiss Institute of Nuclear Research are presented to clarify the picture of SEU response to the high-energy proton environment of Jupiter. It is concluded that the data obtained should remove the concern that nuclear reaction products generated by protons external to the device can cause significant alteration in the device SEU response. The data also show only modest increases in SEU cross section as proton energies are increased up to the upper limits of energy for both the terrestrial and Jovian trapped proton belts.

Nichols, D. K.↗
NASA NTRS1986

Adaptive Quantizer for Burst Synthetic-Aperture Radar

Adaptive quantizer for burst-mode synthetic-aperture radar reduces data rate of return signal. Device, called block floating-point quantizer (BFPQ) basically analog-to-digital converter that covers wide dynamic range and discards appropriate lower order bits. BFPQ is, in effect, digital approximator with automatic gain control. Moves floatingpoint marker binary representation of signal data in accordance with perceived dynamic range. Available step sizes thus limited to multiples of underlying smallest quantization step (represented by lowest order bit). Retains only first K most significant bits of signal; (L,K) BFPQ is one that does K-bit quantization of signal originally quantized to L bits. Quantization error simply difference between actual signal level and its binary approximation. Other potential applications for BFPQ include speech compression and picture data compression.

Joo, T. H.↗
NASA NTRS1985

Research in the design of high-performance reconfigurable systems

The initial control and programming philosophies of the RELAPSE are discussed. A block diagram showing the relationship of the Arithmetic Units (composed of Stages and Bit Processors), to the Functional Units, and other components of the RELAPSE is used to guide this discussion. The latest version of the Bit Processor design is presented. Included is a detailed discussion of the Bit Processor's new scratch pad memory component. The section also clarifies the usage of the Bit Processor's processing registers, and Input/Output functions. The final design phase of the Arithmetic Unit is underway by a study of the Proposed IEEE Floating Point Standard. The decisions on conformation to this standard will be used as inputs into the finalization of the designs of the Bit Processor, Stage, and Arithmetic Units of the RELAPSE.

Slotnick, D. L.↗
NASA NTRS1989

An alternative design for a sparse distributed memory

A new design for a Sparse Distributed Memory, called the selected-coordinate design, is described. As in the original design, there are a large number of memory locations, each of which may be activated by many different addresses (binary vectors) in a very large address space. Each memory location is defined by specifying ten selected coordinates (bit positions in the address vectors) and a set of corresponding assigned values, consisting of one bit for each selected coordinate. A memory location is activated by an address if, for all ten of the locations's selected coordinates, the corresponding bits in the address vector match the respective assigned value bits, regardless of the other bits in the address vector. Some comparative memory capacity and signal-to-noise ratio estimates for the both the new and original designs are given. A few possible hardware embodiments of the new design are described.

Jaeckel, Louis A.↗
NASA NTRS1995

Circuit for high resolution decoding of multi-anode microchannel array detectors

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Kasle, David B.↗
NASA NTRS1995

Fast interrupt platform for extended DOS

Extended DOS offers the unique combination of a simple operating system which allows direct assess to the interrupt tables, 32 bit protected mode access to a 4096 MByte address space, and the use of industry standard C compilers. The drawback is that fast interrupt handling requires both 32 bit and 16 bit versions of each real-time process interrupt handler to avoid mode switches on the interrupts. A set of tools has been developed which automates the process of transforming the output of a standard 32 bit C compiler to 16 bit interrupt code which directly handles the real mode interrupts. The entire process compiles one set of source code via a make file, which boosts productivity by making the management of the compile-link cycle very simple. The software components are in the form of classes written mostly in C. A foreground process written as a conventional application which can use the standard C libraries can communicate with the background real-time classes via a message passing mechanism. The platform thus enables the integration of high performance real-time processing into a conventional application framework.

Duryea, T. W.↗
NASA NTRS1995

Fast interrupt platform for extended DOS

Extended DOS offers the unique combination of a simple operating system which allows direct access to the interrupt tables, 32 bit protected mode access to 4096 MByte address space, and the use of industry standard C compilers. The drawback is that fast interrupt handling requires both 32 bit and 16 bit versions of each real-time process interrupt handler to avoid mode switches on the interrupts. A set of tools has been developed which automates the process of transforming the output of a standard 32 bit C compiler to 16 bit interrupt code which directly handles the real mode interrupts. The entire process compiles one set of source code via a make file, which boosts productivity by making the management of the compile-link cycle very simple. The software components are in the form of classes written mostly in C. A foreground process written as a conventional application which can use the standard C libraries can communicate with the background real-time classes via a message passing mechanism. The platform thus enables the integration of high performance real-time processing into a conventional application framework.

Duryea, T. W.↗
NASA NTRS2003

Characteristics of Single-Event Upsets in a Fabric Switch (ADS151)

Abstract-Two types of single event effects - bit errors and single event functional interrupts - were observed during heavy-ion testing of the AD8151 crosspoint switch. Bit errors occurred in bursts with the average number of bits in a burst being dependent on both the ion LET and on the data rate. A pulsed laser was used to identify the locations on the chip where the bit errors and single event functional interrupts occurred. Bit errors originated in the switches, drivers, and output buffers. Single event functional interrupts occurred when the laser was focused on the second rank latch containing the data specifying the state of each switch in the 33x17 matrix.

Buchner, Stephen↗
NASA NTRS1999

Ka-Band Beam Steering Reflectarray Study

A one-meter diameter, 32 GHz active microstrip reflectarray capable of electronic beam steering has been studied. The 15_500 element array consists of rnicrostrip patch antennas, microstrip phase shifters, and dc bias lines. Specifically, the study focused on the solid-state devices and dc bias layouts for scanning the beam linearly 45 from boresight using 2-bit phase shifters. Three configurations are recommended for the reflectarray with integrated 2-bit phase shifters where the total substrate and cladding mass varies from 8 kg to 14 kg. Additionally, dc power requirements for p-i-n diodes in 1-bit, 2-bit and 3-bit phase shifting circuits are approximately 19 W, 19 W, and 39 W, respectively. The dc power requirement for phase shifters using passive MESFETs is much less than 1 W.

McSpadden, James O.↗
NASA NTRS2005

Ka-Band, MEMS Switched Line Phase Shifters Implemented in Finite Ground Coplanar Waveguide

Ka-band MEMS switched line phase shifters implemented in finite ground coplanar waveguide are described in this paper. The phase shifters are constructed of single-pole double-throw (SPDT) switches with additional reference and phase offset transmission line lengths. The one- and two-bit phase shifters are fabricated on high resistivity (HR) silicon with a dielectric constant, Epsilon(sub T) = 11.7 and a substrate thickness, t = 500microns. The switching architectures integrated within the phase shifters consist of MEMS switches that are doubly anchored cantilever beam capacitive switches with additional high inductive sections (MEMS LC device). The SPDT switch is composed of a T-junction with a MEMS LC device at each output port. The one-bit phase shifter described in this paper has an insertion loss (IL) and return loss (RL) of 0.9 dB and 30 dB while the two-bit described has an IL and RL of 1.8 dB and 30 dB respectively. The one-bit phase shifter's designed offset phase is 22.5deg and actual measured phase shift is 21.8deg. The two-bit phase shifter's designed offset phase is 22.5deg, 45deg, and 67.5deg and the actual measured phase shifts are 21.4deg, 44.2deg, and 65.8deg, respectively.

Scardelletti, Maximilian C.↗
NASA NTRS2009

Hamming and Accumulator Codes Concatenated with MPSK or QAM

In a proposed coding-and-modulation scheme, a high-rate binary data stream would be processed as follows: 1. The input bit stream would be demultiplexed into multiple bit streams. 2. The multiple bit streams would be processed simultaneously into a high-rate outer Hamming code that would comprise multiple short constituent Hamming codes a distinct constituent Hamming code for each stream. 3. The streams would be interleaved. The interleaver would have a block structure that would facilitate parallelization for high-speed decoding. 4. The interleaved streams would be further processed simultaneously into an inner two-state, rate-1 accumulator code that would comprise multiple constituent accumulator codes - a distinct accumulator code for each stream. 5. The resulting bit streams would be mapped into symbols to be transmitted by use of a higher-order modulation - for example, M-ary phase-shift keying (MPSK) or quadrature amplitude modulation (QAM). The novelty of the scheme lies in the concatenation of the multiple-constituent Hamming and accumulator codes and the corresponding parallel architectures of the encoder and decoder circuitry (see figure) needed to process the multiple bit streams simultaneously. As in the cases of other parallel-processing schemes, one advantage of this scheme is that the overall data rate could be much greater than the data rate of each encoder and decoder stream and, hence, the encoder and decoder could handle data at an overall rate beyond the capability of the individual encoder and decoder circuits.

Divsalar, Dariush↗
NASA NTRS2009

Rotary Percussive Auto-Gopher for Deep Drilling and Sampling

The term "rotary percussive auto-gopher" denotes a proposed addition to a family of apparatuses, based on ultrasonic/ sonic drill corers (USDCs), that have been described in numerous previous NASA Tech Briefs articles. These apparatuses have been designed, variously, for boring into, and/or acquiring samples of, rock or other hard, brittle materials of geological interest. In the case of the rotary percussive autogopher, the emphasis would be on developing an apparatus capable of penetrating to, and acquiring samples at, depths that could otherwise be reached only by use of much longer, heavier, conventional drilling-and-sampling apparatuses. To recapitulate from the prior articles about USDCs: A USDC can be characterized as a lightweight, low-power jackhammer in which a piezoelectrically driven actuator generates ultrasonic vibrations and is coupled to a tool bit through a free mass. The bouncing of the free mass between the actuator horn and the drill bit converts the actuator ultrasonic vibrations into sonic hammering of the drill bit. The combination of ultrasonic and sonic vibrations gives rise to a hammering action (and a resulting chiseling action at the tip of the tool bit) that is more effective for drilling than is the microhammering action of ultrasonic vibrations alone. The hammering and chiseling actions are so effective that the size of the axial force needed to make the tool bit advance into soil, rock, or another material of interest is much smaller than in ordinary rotary drilling, ordinary hammering, or ordinary steady pushing. The predecessor of the rotary percussive auto-gopher is an apparatus, now denoted an ultrasonic/sonic gopher and previously denoted an ultrasonic gopher, described in "Ultrasonic/ Sonic Mechanism for Drilling and Coring" (NPO-30291), NASA Tech Briefs Vol. 27, No. 9 (September 2003), page 65. The ultrasonic/sonic gopher is intended for use mainly in acquiring cores. The name of the apparatus reflects the fact that, like a gopher, it periodically stops advancing at the end of the hole to bring excavated material (in this case, a core sample) to the surface, then re-enters the hole to resume the advance of the end of the hole. By use of a cable suspended from a reel on the surface, the gopher is lifted from the hole to remove a core sample, then lowered into the hole to resume the advance and acquire the next core sample.

Bar-Cohen, Yoseph↗
NASA NTRS2007

Self-Advancing Step-Tap Drills

Self-advancing tool bits that are hybrids of drills and stepped taps make it possible to form threaded holes wider than about 1/2 in. (about 13 mm) without applying any more axial force than is necessary for forming narrower pilot holes. These self-advancing stepped-tap drills were invented for use by space-suited astronauts performing repairs on reinforced carbon/carbon space-shuttle leading edges during space walks, in which the ability to apply axial drilling forces is severely limited. Self-advancing stepped-tap drills could also be used on Earth for making wide holes without applying large axial forces. A self-advancing stepped-tap drill (see figure) includes several sections having progressively larger diameters, typically in increments between 0.030 and 0.060 in. (between about 0.8 and about 1.5 mm). The tip section, which is the narrowest, is a pilot drill bit that typically has a diameter between 1/8 and 3/16 in. (between about 3.2 and about 4.8 mm). The length of the pilot-drill section is chosen, according to the thickness of the object to be drilled and tapped, so that the pilot hole is completed before engagement of the first tap section. Provided that the cutting-edge geometry of the drill bit is optimized for the material to be drilled, only a relatively small axial force [typically of the order of a few pounds (of the order of 10 newtons)] must be applied during drilling of the pilot hole. Once the first tap section engages the pilot hole, it is no longer necessary for the drill operator to apply axial force: the thread engagement between the tap and the workpiece provides the axial force to advance the tool bit. Like the pilot-drill section, each tap section must be long enough to complete its hole before engagement of the next, slightly wider tap section. The precise values of the increments in diameter, the thread pitch, the rake angle of the tap cutting edge, and other geometric parameters of the tap sections must be chosen, in consideration of the workpiece material and thickness, to prevent stripping of threads during the drilling/tapping operation. A stop-lip or shoulder at the shank end of the widest tap section prevents further passage of the tool bit through the hole.

Pettit, Donald R.↗
NASA NTRS2010

Rapid Active Sampling Package

A field-deployable, battery-powered Rapid Active Sampling Package (RASP), originally designed for sampling strong materials during lunar and planetary missions, shows strong utility for terrestrial geological use. The technology is proving to be simple and effective for sampling and processing materials of strength. Although this originally was intended for planetary and lunar applications, the RASP is very useful as a powered hand tool for geologists and the mining industry to quickly sample and process rocks in the field on Earth. The RASP allows geologists to surgically acquire samples of rock for later laboratory analysis. This tool, roughly the size of a wrench, allows the user to cut away swaths of weathering rinds, revealing pristine rock surfaces for observation and subsequent sampling with the same tool. RASPing deeper (.3.5 cm) exposes single rock strata in-situ. Where a geologist fs hammer can only expose unweathered layers of rock, the RASP can do the same, and then has the added ability to capture and process samples into powder with particle sizes less than 150 microns, making it easier for XRD/XRF (x-ray diffraction/x-ray fluorescence). The tool uses a rotating rasp bit (or two counter-rotating bits) that resides inside or above the catch container. The container has an open slot to allow the bit to extend outside the container and to allow cuttings to enter and be caught. When the slot and rasp bit are in contact with a substrate, the bit is plunged into it in a matter of seconds to reach pristine rock. A user in the field may sample a rock multiple times at multiple depths in minutes, instead of having to cut out huge, heavy rock samples for transport back to a lab for analysis. Because of the speed and accuracy of the RASP, hundreds of samples can be taken in one day. RASP-acquired samples are small and easily carried. A user can characterize more area in less time than by using conventional methods. The field-deployable RASP used a Ni/Cad rechargeable battery. Power usage was less than 1 Wh/ cm3 even when sampling strong basalts, so many samples could be taken on a single battery charge.

Peters, Gregory↗
NASA NTRS2005

Powder-Collection System for Ultrasonic/Sonic Drill/Corer

A system for collecting samples of powdered rock has been devised for use in conjunction with an ultrasonic/sonic drill/corer (USDC) -- a lightweight, lowpower apparatus designed to cut into, and acquire samples of, rock or other hard material for scientific analysis. The USDC includes a drill bit, corer, or other tool bit, in which ultrasonic and sonic vibrations are excited by an electronically driven piezoelectric actuator. The USDC advances into the rock or other material of interest by means of a hammering action and a resulting chiseling action at the tip of the tool bit. The hammering and chiseling actions are so effective that unlike in conventional twist drilling, a negligible amount of axial force is needed to make the USDC advance into the material. Also unlike a conventional twist drill, the USDC operates without need for torsional restraint, lubricant, or a sharp bit. The USDC generates powder as a byproduct of the drilling or coring process. The purpose served by the present samplecollection system is to remove the powder from the tool-bit/rock interface and deliver the powder to one or more designated location(s) for analysis or storage

Sherrit, Stewart↗
NASA NTRS2011

Methodology and method and apparatus for signaling with capacity optimized constellations

Communication systems having transmitter, includes a coder configured to receive user bits and output encoded bits at an expanded output encoded bit rate, a mapper configured to map encoded bits to symbols in a symbol constellation, a modulator configured to generate a signal for transmission via the communication channel using symbols generated by the mapper. In addition, the receiver includes a demodulator configured to demodulate the received signal via the communication channel, a demapper configured to estimate likelihoods from the demodulated signal, a decoder that is configured to estimate decoded bits from the likelihoods generated by the demapper. Furthermore, the symbol constellation is a capacity optimized geometrically spaced symbol constellation that provides a given capacity at a reduced signal-to-noise ratio compared to a signal constellation that maximizes d.sub.min.

Barsoum, Maged F.↗