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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Feasibility study: Replacement of the inoperative decommutating buffer subsystem for the instrumentation checkout complex in the Quality and Reliability Assurance Laboratory

A general purpose computer system, that is necessary for replacement of the present inoperative signal decommutator special purpose computer subsystem is described. The present decommutator subsystem has a very poor history of reliability and since April 1970, it has become inoperative because the core memory cannot be repaired. Functions of the present signal, decommutator subsystem are to receive, demultiplex, record in real time, playback in real time, and output to the SDS-930 control computer for analysis of the telemetry data. Recommendations for replacement of the inoperative telemetry decommutator subsystem are for the purchase of a mini-computer.

Hilliard, J. W.↗
NASA NTRS1975

Buffer control unit for computer communications

Unit provides character echoing for keyboard display, parity and syndrome generation (error detection), half or full data-packet generation, automatic retransmission of packets, and keyboard lock-up.

Okinaka, A. K.↗
NASA NTRS1978

Stress intensity factors of composite orthotropic plates containing periodic buffer strips

The fracture problem of laminated plates which consist of bonded orthotropic layers is studied. The fields equations for an elastic orthotropic body are transformed to give the displacement and stress expressions for each layer or strip. The unknown functions in these expressions are found by satisfying the remaining boundary and continuity conditions. A system of singular integral equations is obtained from the mixed boundary conditions. The singular behavior around the crack tip and at the bimaterial interface is studied. The stress intensity factors are computed for various material combinations and various crack geometries. The results are discussed and are compared with those for isotropic materials.

Delale, F.↗
NASA NTRS1982

Queueing analysis of synchronous time division multiplexing with individual source buffering

Synchronous time division multiplexing is analyzed. Packets of information arrive at the system as a compound Poisson process, and are transmitted only during individual periodic intervals. Packet arrivals are blocked (lost) if the system has a finite capacity and is congested. Using the theory of semiregenerative processes, the distribution of the number of packets in the system (system size) is found. This nonstationary distribution is used to determine the complete system behavior, including the delay distributions, the blocking probability, and the density of the system size at arrival instants. Numerical examples illustrate applications of the results given.

Clare, L.↗
NASA NTRS1981

Dish-mounted latent heat buffer storage

Dish-mounted latent heat storage subsystems for Rankine, Brayton, and Stirling engines operating at 427 C, 816 C, and 816 C respectively are discussed. Storage requirements definition, conceptual design, media stability and compatibility tests, and thermal performance analyses are considered.

Manvi, R.↗
NASA NTRS1991

Deep FIFO Surge Buffer

First-in/first-out (FIFO) temporarily stores short surges of data generated by data-acquisition system at excessively high rate and releases data at lower rate suitable for processing by computer. Size and complexity reduced while capacity enhanced by use of newly developed, sophisticated integrated circuits and by "byte-folding" scheme doubling effective depth and data rate.

Temple, Gerald↗
NASA NTRS1993

Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer

Multiple instruction rollback (MIR) is a technique to provide rapid recovery from transient processor failures and was implemented in hardware by researchers and slow in mainframe computers. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs were also developed which remove rollback data hazards directly with data flow manipulations, thus eliminating the need for most data redundancy hardware. Compiler-assisted techniques to achieve multiple instruction rollback recovery are addressed. It is observed that data some hazards resulting from instruction rollback can be resolved more efficiently by providing hardware redundancy while others are resolved more efficiently with compiler transformations. A compiler-assisted multiple instruction rollback scheme is developed which combines hardware-implemented data redundancy with compiler-driven hazard removal transformations. Experimental performance evaluations were conducted which indicate improved efficiency over previous hardware-based and compiler-based schemes. Various enhancements to the compiler transformations and to the data redundancy hardware developed for the compiler-assisted MIR scheme are described and evaluated. The final topic deals with the application of compiler-assisted MIR techniques to aid in exception repair and branch repair in a speculative execution architecture.

Alewine, Neal Jon↗
NASA NTRS1992

Processor architecture and data buffering

A set of architectures from three major architecture families: stack, register, and memory-to-memory is discussed. It is shown that scalable architectures are not applicable for low-density technologies because they require at least 32 words of local memory. Software support is shown to be capable of bridging the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local memory allocated interprocedurally outperforms scalable architectures with equal sizes local memories and even some with larger size local memories. The performance advantage of unscalable architectures becomes significant when in addition to quality compile-time support, a small cache is added to an unscalable architecture. A 32-register architecture with 512 byte cache executes 20 percent less cycles when compared with an 8-set multiple overlapping set organization.

Mulder, Hans↗
NASA NTRS1992

Explosive volcanism and the graphite-oxygen fugacity buffer on the parent asteroid(s) of the ureilite meteorites

A new model of the production of the uniformly low plagioclase and Al contents of ureilites is proposed. It is argued that those contents are consequences of widespread explosive volcanism during the evolution of the parent asteroid(s). It is noted that the great abundance of graphite on the ureilite asteroid(s) made them ideal sites for explosive volcanism driven by oxidation of graphite in partial melts ascending within the asteroid(s).

Warren, Paul H.↗
NASA NTRS1990

CMOS output buffer wave shaper

As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

Albertson, L.↗