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All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

4H-SiC UV Photo Detector with Large Area and Very High Specific Detectivity

Pt/4H-SiC Schottky photodiodes have been fabricated with the device areas up to 1 sq cm. The I-V characteristics and photo-response spectra have been measured and analyzed. For a 5 mm x 5 mm area device leakage current of 1 x 10(exp 15)A at zero bias and 1.2 x 10(exp 14)A at -IV have been established. The quantum efficiency is over 30% from 240nm to 320nm. The specific detectivity, D(sup *), has been calculated from the directly measured leakage current and quantum efficiency data and are shown to be higher than 10(exp 15) cmHz(sup 1/2)/W from 210nm to 350nm with a peak D(sup *) of 3.6 x 10(exp 15)cmH(sup 1/2)/W at 300nm.

Yan, Feng↗
NASA NTRS2004

Web Growth Used to Confine Screw Dislocations to Predetermined Lateral Positions in 4H-SiC Epilayers

Silicon-carbide- (SiC-) based power devices could enable substantial aerospace electronics benefits over today's silicon-based electronics. However, present-day SiC wafers contain electrically harmful dislocations (including micropipes) that are unpredictably distributed in high densities across all commercial 4H- and 6H-SiC wafers. The NASA Glenn Research Center recently demonstrated a crystal growth process that moves SiC wafer dislocations to predetermined lateral positions in epitaxial layers so that they can be reproducibly avoided during subsequent SiC electronic device fabrication. The process starts by reactive ion etching mesa patterns with enclosed trench regions into commercial on-axis (0001) 4H- or 6H-SiC substrates. An example of a pregrowth mesa geometry with six enclosed triangular-shaped trench regions is shown. After the etch mask is stripped, homoepitaxial growth is carried out in pure stepflow conditions that enable thin cantilevers to grow laterally from the tops of mesas whose pregrowth top surfaces are not threaded by substrate screw dislocations. The image in the bottom figure shows the postgrowth structure that forms after the lateral cantilevers expand to coalesce and completely roof over each of the six triangular trench regions. Atomic force microscope (AFM) measurements of the roof revealed that three elementary screw dislocation growth spirals, each shown in the AFM insets of the bottom image on the previous page, formed in the film roof at three respective points of cantilever film coalescence. The image above shows the structure following an etch in molten potassium hydroxide (KOH) that produced surface etch pits at the dislocation defects. The larger KOH etch pits--S1, S2, and S3--shown in this image correspond to screw dislocations relocated to the final points of cantilever coalescence. The smaller KOH etch pits are consistent with epilayer threading edge dislocations from the pregrowth substrate mesa (P1, P3, and P4) and a final cantilever coalescence point (P2). No defects (i.e., no etch pits) are observed in other cantilevered portions of the film surface. On the basis of the principle of dislocation Burgers vector conservation, we hypothesize that all vertically propagating substrate dislocations in an enclosed trench region become combined into a single dislocation in the webbed film roof at the point of final roof coalescence. The point of final roof coalescence, and therefore the lateral location of a webbed roof dislocation, can be designed into the pregrowth mesa pattern. Screw dislocations with predetermined lateral positions can then be used to provide the new growth steps necessary for growing a 4H/6H-SiC epilayer with a lower dislocation density than the substrate. Devices fabricated on top of such films can be positioned to avoid the preplaced dislocations.

Powell, J. Anthony↗
NASA NTRS2006

Static and Switching Characteristics of a 4H-SiC Based BJT to 200 C

Static curves and resistive load switching characteristics of a 600 V, 4 A rated, SiC-based NPN bipolar power transistor (BJT) were observed at selected temperatures from 23 to 200 C. All testing was done in a pulse mode at low duty cycle (approx. 0.1 percent). Turn-on was driven by an adjustable base current pulse and turn-off was accelerated by a negative base voltage pulse of either 7 or 0.6 V. Switching observations were done at base drive currents (I(sub B)) up to 400 mA and collector currents (I(sub C)) up to 4 A, using a 100 OMEGA non-inductive load. At I(sub B) = 400 mA and I(sub C) = 4 A, turn-on times typically varied from 81 to 97 ns, over temperatures from 23 to 200 C. As expected, lowering the base drive greatly extended the turn-on time. Similarly, decreasing the load current to I(sub C) = 1 A with I(sub B) = 400 mA produced turn-on times as short as 30 ns. Over the 23 to 200 C range, with I(sub B) = 400 mA and I(sub C) = 4 A, turn-off times were in the range of 61 to 77 ns with the 7 V sweep-out and 130 to 150 ns with the 0.6 V sweep-out. At a fixed temperature and I(sub C), the turn-off time decreased slightly with decreasing I(sub B), for I(sub B) sufficient to still provide full turn-on. The ratio of conduction to switching losses is estimated, based on the observed I(sub C) transition times and static curves. An estimate at 200 kHz and a 50 percent duty cycle shows that under practicable conditions the two losses can be comparable. Hence the evidence obtained does not support the occasionally voiced concern of necessarily unacceptably high conduction losses in SiC-based BJTs.

Niedra, Janis M.↗
NASA NTRS2006

Switching Characteristics of a 4H-SiC Based Bipolar Junction Transistor to 200 C

Static curves and resistive load switching characteristics of a 600 V, 4 A rated, SiC-based NPN bipolar power transistor (BJT) were observed at selected temperatures from room to 200 C. All testing was done in a pulse mode at low duty cycle (approx.0.1 percent). Turn-on was driven by an adjustable base current pulse and turn-off was accelerated by a negative base voltage pulse of 7 V. These base drive signals were implemented by 850 V, gated power pulsers, having rise-times of roughly 10 ns, or less. Base charge sweep-out with a 7 V negative pulse did not produce the large reverse base current pulse seen in a comparably rated Si-based BJT. This may be due to a very low charge storage time. The decay of the collector current was more linear than its exponential-like rise. Switching observations were done at base drive currents (I(sub B)) up to 400 mA and collector currents (I(sub C)) up to 4 A, using a 100 Omega non-inductive load. At I(sub B) = 400 mA and I(sub C) = 4 A, turn-on times typically varied from 80 to 94 ns, over temperatures from 23 to 200 C. As expected, lowering the base drive greatly extended the turn-on time. Similarly, decreasing the load current to I(sub C) = 1 A with I(sub B) = 400 mA produced turn-on times as short as 34 ns. Over the 23 to 200 C range, with I(sub B) = 400 mA and I(sub C) = 4 A, turn-off times were in the range of 72 to 84 ns with the 7 V sweep-out.

Niedra, Janis M.↗
NASA NTRS2002

Glennan Microsystems Initiative

During the 2001-2002 award period, we performed research on Pt/Ti/bare 6H-SiC and bare 4H-SiC interfaces in order to identify their electronic properties as a function of surface preparation. The overall aim of this work is to optimize the electronic properties of metal contacts to SiC as well as the active SiC material itself as a function of surface preparation and subsequent processing. Initially, this work has involved identifying bare surface, subsurface, and metal induced gap states at the metal-SiC contact and correlating energies and densities of deep levels with Schottky barrier heights. We used low energy electron-excited nanoluminescence (LEEN) spectroscopy, X-ray photoemission spectroscopy (XPS), and Secondary Ion Mass Spectrometry (SIMS) in order to correlate electronic states and energy bands with chemical composition, bonding, and crystal structure. A major development has been the discovery of polytype transformations that occur in 4H-SiC under standard microelectronic process conditions used to fabricate SiC devices. Our results are consistent with the stacking fault generation, defect formation, and consequent degradation of SiC recently reported for state-of-the-art ABB commercial diodes under localized electrical stress. Our results highlight the importance of -optimizing process conditions and material properties - anneal times, temperatures and doping to control such structural changes within epitaxial SiC layers. Thus far, we have established threshold times and temperatures beyond which 4H-SiC exhibits 3C-SiC transformation bands for a subset of dopant concentrations and process conditions. On the basis of this temperature time behavior, we have been able to establish an activation energy of approximately 2.5 eV for polytype transformation and dislocation motion. Work continues to establish the fundamental mechanisms underlying the polytype changes and its dependence on material parameters.

Brillson, Leonard J.↗
NASA NTRS1996

Effect of Tilt Angle on the Morphology of SiC Epitaxial Films Grown on Vicinal (0001) SiC Substrates

In this study of 4H-SiC and 6H-SiC epitaxial films we found that film morphology was strongly dependent on the tilt angle of the substrate. Large surface steps (up to 25 nm high) due to step bunching were more prevalent at smaller tilt angles. Also, 4H films were more susceptible than 6H to 3C-SiC inclusions during growth. The lateral growth of steps from screw dislocations in low-tilt-angle substrates demonstrated that step bunching on the atomic scale was anisotropic with respect to growth direction for both 4H-SiC and 6H-SiC. A model explaining this behavior is presented. We observed and directly measured the Burgers vector of a 'super' screw dislocation in a 6H-SiC epilayer.

Powell, J. A.↗
NASA NTRS1997

Process-Induced Morphological Defects in Epitaxial CVD Silicon Carbide

Silicon carbide (SiC) semiconductor technology has been advancing rapidly, but there are numerous crystal growth problems that need to be solved before SiC can reach its full potential. Among these problems is a need for an improvement in the surface morphology of epitaxial films that are grown to produce device structures. Various processes before and during epilayer growth lead to the formation of morphological defects observed in SiC epilayers grown on SiC substrates. In studies of both 6H and 4H-SiC epilayers, atomic force microscopy (AFM) and other techniques have been used to characterize SiC epilayer surface morphology. In addition to the well-known micropipe defect, SiC epilayers contain growth pits, triangular features (primarily) in 4H-SiC, and macro step due to step bunching. In work at NASA Lewis, it has been found that factors contributing to the formation of some morphological defects include: defects in the substrate bulk, defects in the substrate surface caused by cutting and polishing the wafer, the tilt angle of the wafer surface relative to the basal plane, and growth conditions. Some of these findings confirm results of other research groups. This paper presents a review of published and unpublished investigations into processes that are relevant to epitaxial film morphology.

Powell, J. A.↗
NASA NTRS2010

A Novel Tungsten-Nickel Alloy Ohmic Contact to SiC at 900 C

A novel tungsten-nickel ohmic contact metallization on 4H-SiC and 6H-SiC capable of surviving temperatures as high as 900 C is reported. Preliminary results revealed the following: 1) ohmic contact on n-type 4H-SiC having net doping levels (Nd's) of 1.4 and 2 x 10(exp 19) per cubic centimeter, with specific contact resistances rhosNd's of 7.69 x 10(exp -4) and 5.81 x 10(exp -4) OMEGA (raised dot) square centimeters, respectively, after rapid thermal annealing (RTA), and 5.9 x 10(exp -3) and 2.51 x 10(exp -4) OMEGA (raised dot) square centimeters, respectively, after subsequent soak at 900 C for 1 h in argon, and 2) ohmic contact on n- and p-type 6H-SiC having Nd > 2 x 10(exp 19) and Na > 1 x 10(exp 20) per cubic centimeter, with rhosNd = 5 x 10(exp -5) and rhosNa = 2 X 10(exp -4) OMEGA (raised dot) square centimeter, respectively, after RTA, and rhosNd = 2.5 x 10 (exp -5) and rhosNa = 1.5 x 10(exp -4) OMEGA (raised dot) square centimeter after subsequent treatment at 900 C for 1 h in argon, respectively.

Okojie, Robert S.↗
NASA NTRS2006

CFD Growth of 3C-SiC on 4H/6H Mesas

This article describes growth and characterization of the highest quality reproducible 3C-SiC heteroepitaxial films ever reported. By properly nucleating 3C-SiC growth on top of perfectly on-axis (0001) 4H-SiC mesa surfaces completely free of atomic scale steps and extended defects, growth of 3C-SiC mesa heterofilms completely free of extended crystal defects can be achieved. In contrast, nucleation and growth of 3C-SiC mesa heterofilms on top of 4H-SiC mesas with atomic-scale steps always results in numerous observable dislocations threading through the 3C-SiC epilayer. High-resolution X-ray diffraction and transmission electron microscopy measurements indicate non-trivial in-plane lattice mismatch between the 3C and 4H layers. This mismatch is somewhat relieved in the step-free mesa case via misfit dislocations confined to the 3C/4H interfacial region without dislocations threading into the overlying 3C-SiC layer. These results indicate that the presence or absence of steps at the 3C/4H heteroepitaxial interface critically impacts the quality, defect structure, and relaxation mechanisms of single-crystal heteroepitaxial 3C-SiC films.

Neudeck, Philip G.↗
NASA NTRS1998

Gaseous Etching for Characterization of Structural Defects in Silicon Carbide Single Crystals

Single crystal SiC substrates were subjected to high-temperature H2/C3H8 gaseous etches. The etches resulted in a variety of surface features on 4H-SiC substrates that included elongated hillocks from 10 to more than 100 microns in length by a few microns in width. In some 4H- and 6H-SiC substrates, the etches resulted in a continuous coverage of macrosteps. We conclude that the morphology observed after the etching process is influenced by the local Si-C bilayer stacking sequence on the surface of off-(0001)oriented substrates. A model is presented for the formation of the hillocks, based on localized transformations of the 4H substrates during the high temperature etch process.

Powell, J. A.↗
NASA NTRS2001

Ab-Initio Description and Prediction of Properties of Carbon-Based and Other Non-Metallic Materials

We have resolved the long-standing problem consisting of 30%-50% theoretical underestimates of the band gaps of non-metallic materials. We describe the Bagayoko, Zhao, and Williams (BZW) method that rigorously circumvents the basis-set and variational effect presumed to be a cause of these underestimates. We present ab-initio, computational results that are in agreement with experiment for diamond (C), silicon (Si), silicon carbides (3C-SiC and 4H-SiC), and other semiconductors (GaN, BaTiO3, AlN, ZnSe, ZnO). We illustrate the predictive capability of the BZW method in the case of the newly discovered cubic phase of silicon nitride (c-Si3N4) and of selected carbon nanotabes [(10,0), and (8,4)]. Our conclusion underscores the inescapable need for the BZW method in ab-initio calculations that employ a basis set in a variational approach. Current nanoscale trends amplify this need. We estimate that the potential impact of applications of the BZW method in advancing our understanding of nonmetallic materials, in informing experiment, and particularly in guiding device design and fabrication is simply priceless.

Bagayoko, D.↗
NASA NTRS2002

Method for Growing Low-Defect Single Crystal Heteroepitaxial Films

A method is disclosed for growing high-quality low-defect crystal films heteroepitaxially on substrates that are different than the crystal films. The growth of the first two heteroepitaxial bilayers is performed on a first two-dimensional nucleate island before a second growth of two-dimensional nucleation is allowed to start. The method is particularly suited for the growth of 3C-SiC, 2H-AlN, or 2H-GaN on 6H-SiC, 4H-SiC, or silicon substrates.

Powell, J. Anthony↗
NASA NTRS2002

Growth of Defect-Free 3C-Sic on 4H- and 6H-SIC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3C-SiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (Delta/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS2004

Measurement of Thin Film Integrated Passive Devices on SiC through 500 C

Wireless communication in jet engines and high temperature industrial applications requires FD integrated circuits (RFICs) on wide bandgap semiconductors such as Silicon Carbide (SiC). In this paper, thin-film NiCr resistors, MIM capacitors, and spiral inductors are fabricated on a high purity semi-insulating 4H-SiC substrate. The devices are experimentally characterized through 50 GHz at temperatures of up to 500 C and the equivalent circuits are deembedded from the measured data. It is shown that the NiCr resistors are stable within 10% to 300 C while the capacitors have a value stable within 10% through 500 C.

Schwartz, Zachary D.↗
NASA NTRS2004

Growth and Characterization of Silicon-Carbide Hetero-Polytype Structures

Films discussed in this repok were deposited at NASA Glenn Research Center on on- orientation 4H-Sic substrates. Substrates were patterned in order to form mesa structures of different shapes and sizes. The nominal thickness of the 3C-Sic film was approximately 10 microns although the thickness could change considerably between defect-free and defected mesa structures. The primary objective was to identify defect structures in defect-free mesas and in particular determine the degree and mode of strain relaxation in 3C films with thickness exceeding critical thickness.

Skowronski, Marek↗
NASA NTRS2005

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Niedra, Janis M.↗
NASA NTRS2005

Improved Method of Manufacturing SiC Devices

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Okojie, Robert S.↗
NASA NTRS2001

Growth of Defect-Free 3C-SiC on 4H- and 6H-SiC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3CSiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (delta a/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗