Search NASA⌕ Search

SEARCH · Search NASA

Results for “ASIC”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

A 20 Gbps Data Transmitting ASIC with PAM4 for Particle Physics Experiments

We present the design principle and test results of a data transmitting ASIC, GBS20, for particle physics experiments. The goal of GBS20 will be an ASIC that employs two serializers each from the 10.24 Gbps lpGBT SerDes, sharing the PLL also from lpGBT. A PAM4 encoder plus a VCSEL driver will be implemented in the same die to use the same clock system, eliminating the need of CDRs in the PAM4 encoder. This way the transmitter module, GBT20, developed using the GBS20 ASIC, will have the exact lpGBT data interface and transmission protocol, with an output up to 20.48 Gbps over one fiber. With PAM4 embedded FPGAs at the receiving end, GBT20 will halve the fibers needed in a system and better use the input bandwidth of the FPGA. A prototype, GBS20v0 is fabricated using a commercial 65 nm CMOS technology. This prototype has two serializers and a PAM4 encoder sharing the lpGBT PLL, but no user data input. An internal PRBS generator provides data to the serializers. GBS20v0 is tested barely up to 20.48 Gbps. With lessons learned from this prototype, we are designing the second prototype, GBS20v1, that will have 16 user data input channels each at 1.28 Gbps. We present the design concept of the GBS20 ASIC and the GBT20 module, the preliminary test results, and lessons learned from GBS20v0 and the design of GBS20v1 which will be not only a test chip but also a user chip with 16 input data channels.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented, along with a demonstrative example of using Spacely to test a pixel detector readout ASIC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Design and performance of the Fermilab Constant Fraction Discriminator ASIC

Here, we present the design and performance characterization results of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout low gain avalanche detector (LGAD) signals by directly using a constant fraction discriminator (CFD) to measure signal arrival time. Silicon detectors with time resolutions less than 30ps will play a critical role in future collider experiments, and LGADs have been demonstrated to provide the required time resolution and radiation tolerance for many such applications. The FCFD has a specially designed discriminator that is robust against amplitude variations of the signal from the LGAD that normally requires an additional correction step when using a traditional leading edge discriminator. The application of the CFD directly in the ASIC promises to be more reliable and reduces the complication of evolving time-walk corrections throughout the operational lifetime of the detector system. We will present a summary of the measured performance of the FCFD for input signals generated by internal charge injection, LGAD signals from an infrared laser, and LGAD signals from minimum-ionizing particles. The mean time response for LGAD signals with charge ranging between 5 and 26 fC has been measured to vary no more than 10ps, orders of magnitude more stable than an uncorrected leading edge discriminator based measurement, and effectively removes the need for any additional time-walk correction. The measured contribution to the time resolution from the FCFD ASIC is found to be 10ps for signals with charge above 20fC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Multi-channel front-end ASIC for a 3D position-sensitive detector

Arrays of 3D position-sensitive detectors (3DPSD), operating at room temperature and using cadmium zinc telluride (CZT) and thallium bromide (TIBr) sensors, are suitable for gamma-ray spectrometry in many applications. One detector configuration, the 3D position-sensitive Virtual Frisch-Grid detector (VFG), is particularly advantageous for integrating into large area arrays. The signals generated inside each detector of the array are captured with the anode, cathode and four pads that enable the reconstruction of the position and energy of the ionizing interaction by measurements of amplitude and timing of the signals. For these applications, a low-noise front-end ASIC has been developed, capable of processing bipolar signals (needed because of AC-coupling of certain electrodes). The ASIC can be coupled to an ADC in order to form a compound “waveform digitizer” capable of post-processing the analog signals and determining amplitude and timing information. This paper describes a 32-channel front-end ASIC that is suitable for reading out a 3 × 3 or 4 × 4 element matrix in the VFG configuration. Each channel is composed of a low-noise charge amplifier with an adaptive continuous reset feedback circuit suitable for both positive and negative charge, a first order shaper and a single-to-differential converter output stage. Voltage and current references are all internally generated by 10-bit DACs and the chip is fully controllable with the I 2 C communication protocol. The readout channel response has been verified using the implemented injection circuit. Linear behavior up to ~75 ke ± with the gain of ~80 mV/fC, and up to ~200 ke ± with the gain of ~30 mV/fC was demonstrated. In conclusion, the first test result waveforms using a 137 Cs radioactive source on a 5 × 5 × 12 mm 3 TIBr crystal are reported.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Studies in pulse shape discrimination for an optimized ASIC design

The continued advancements of Silicon Photomultipliers (SiPMs) have made them viable photosensors for low recoil energy Pulse Shape Discrimination (PSD) between fast neutron and gamma interactions when coupled to an appropriate scintillator. At the same time, the large number of channels in a typical array calls for the development of low-cost and low-power electronics. A custom integrated circuit (ASIC) is an ideal solution for this purpose. To assess the requirements for such an ASIC, studies were performed using two scintillators, Stilbene and EJ-276, coupled to a 6 x 6 mm SiPM from Onsemi. We demonstrate that both scintillators are viable for performing PSD for interaction energies from 100 keV to several MeV while optimizing the integration periods used in the PSD metric. These measurements inform the design parameters of the ASIC under development.

Si-PMTs↗
DOE OSTI2024

Performance of a second generation of the Fermilab Constant Fraction Discriminator ASIC for time-stamping long-strip AC-LGAD sensors.

We present the design and performance characterization results of the second generation of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout AC-coupled low gain avalanche detector (AC-LGAD) sensors. This study presents the performance of the ASIC which was optimized specifically for reading out strip AC-LGAD sensors designed for ePIC experiment at EiC. Performance was measured using charge injection and particle beams with prototype AC-LGAD sensors wirebonded to the FCFD ASIC.

Apresyan, A.↗
DOE OSTI2023

A 32-channels readout ASIC for X-ray spectrometry and tracking in the GAPS experiment

Here this work describes the architecture and the experimental results from the characterization of a 32-channels mixed-signal Application-Specific Integrated Circuit (ASIC) developed for the readout of the lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full custom integrated circuit, named SLIDER32 (32-channels Si-LI DEtector Readout) ASIC, has been produced in a commercial 180 nm CMOS technology. The ASIC is comprised of 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit SAR ADC and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

CMS High Granularity Calorimeter ECON-D ASIC overview and radiation testing results

The Compact Muon Solenoid (CMS) Experiment’s High Granularity Calorimeter (HGCAL) upgrade replaces the CMS electromagnetic and hadronic endcap calorimeters in preparation for the high-rate and high-radiation environment of the High Luminosity LHC. To effectively use the over 6 million channels of this highly-segmented “imaging” calorimeter, CMS is pioneering very front-end data compression with the Endcap Concentrator (ECON) ASICs – the ECON-T for the trigger path and the ECON-D for the data path. These 65 nm CMOS ASICs are radiation tolerant (200 Mrad) and low-power (< 2.5 mW/channel). In June 2023, we received the first full-functionality prototype of the data path concentrator ASIC, the ECON-D-P1. This talk will present an overview of the ECON-D-P1, summarize functionality and system testing, and present results from both Total Ionizing Dose (TID) and Single Event Effect (SEE) testing campaigns completed in summer 2023, validating the ECON-D radiation tolerant performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗
DOE OSTI2025

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented in brief. Current documentation is available at https://github.com/SpacelyProject/spacely-docs.

Quinn, Adam [Fermilab]↗
DOE OSTI2026

Two 28-nm front-end ASICs for ultra-fine spatial resolution and precision timing to be 3D integrated with 12 LGADs

The 3DIntSenS Collaboration—a joint effort between SLAC, Fermilab, and LLNL—is developing enabling technologies for next-generation radiation imaging detectors that combine ultra-fine spatial resolution (about 10 µm) with precision timing (<20 ps), while maintaining low power <1 W/cm2 and high data throughput. The approach leverages 3D integration between advanced CMOS readout ASICs and finely pixelated LGAD sensors to achieve the performance and scalability required for large-area, high-rate applications. High-granularity, precision-timing detectors are essential for scientific advances in HEP, NP, BES, and FES, but widespread adoption is limited by the cost and complexity of 3D integration. To close this gap, the collaboration is developing LGAD sensors compatible with 12-inch commercial CMOS processes, enabling cost-effective integration with high-performance ASICs under development. We present two 28 nm CMOS ASIC prototypes, including a low-jitter front end, and in-pixel TDC demonstrating sub-10 ps timing resolution. These advances represent a critical step toward scalable, high-resolution radiation imaging systems for future scientific instrumentation.

England, Troy [Fermilab] (ORCID:0000000154405255)↗
DOE OSTI2026

Two 28-nm front-end ASICs for ultra-fine spatial resolution and precision timing to be 3D integrated with 12 LGADs

The 3DIntSenS Collaboration—a joint effort between SLAC, Fermilab, and LLNL—is developing enabling technologies for next-generation radiation imaging detectors that combine ultra-fine spatial resolution (about 10 µm) with precision timing (<20 ps), while maintaining low power <1 W/cm2 and high data throughput. The approach leverages 3D integration between advanced CMOS readout ASICs and finely pixelated LGAD sensors to achieve the performance and scalability required for large-area, high-rate applications. High-granularity, precision-timing detectors are essential for scientific advances in HEP, NP, BES, and FES, but widespread adoption is limited by the cost and complexity of 3D integration. To close this gap, the collaboration is developing LGAD sensors compatible with 12-inch commercial CMOS processes, enabling cost-effective integration with high-performance ASICs under development. We present two 28 nm CMOS ASIC prototypes, including a low-jitter front end, and in-pixel TDC demonstrating sub-10 ps timing resolution. These advances represent a critical step toward scalable, high-resolution radiation imaging systems for future scientific instrumentation.

England, Troy [Fermilab] (ORCID:0000000154405255)↗
DOE OSTI2026

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences↗
NASA NTRS1990

Using advanced microelectronic test chips to qualify ASIC's for space

Qualification procedures for complex integrated circuits are being developed under a U.S. government program known as Qualified Manufacturing Lines (QML). This effort is focused on circuits designed by IC manufacturers and has not addressed application specific IC's (ASIC's) designed at system houses. The qualification procedures described here are intended to be responsive to the needs of system houses who design their own ASIC's and have them fabricated at Silicon foundries. A particular focus of this presentation will be the use of the TID (total Ionizing Dose) Chip to evaluate CMOS foundry processes and to provide parameters for circuit simulators. This chip is under development as a standard chip for qualifying the total dose aspects of ASIC's. The benefits of standardization are that the results will be well understood and easy to interpret. Data is presented and compared for 1.6 micron and 3.0 micron CMOS. The data shows that 1.6 micron CMOS is significantly harder than 3.0 micron CMOS. Two failure modes are explored: (1) the radiation-induced degradation of timing delays; and (2) radiation-induced leakage currents.

Buehler, M. G.↗
NASA NTRS1994

SODR Memory Control Buffer Control ASIC

The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

Hodson, Robert F.↗
NASA NTRS1997

Burst Mode ASIC-Based Modem

The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

Source record↗
NASA NTRS2011

A Radiation Hard Multi-Channel Digitizer ASIC for Operation in the Harsh Jovian Environment

In 1995, the Galileo spacecraft arrived at Jupiter to conduct follow-up experiments on pathfinder Pioneer and key Voyager discoveries especially at Io, Europa, Ganymede and Callisto. These new observations helped expand our scientific knowledge of the prominent Galilean satellites; studies revealed diversity with respect to their geology, internal structure, evolution and degree of past and present activity. Jupiter's diverse Galilean satellites, of which three are believed to harbor internal oceans, are central to understanding the habitability of icy worlds. Galileo provided for the first time compelling evidence of a near-surface global ocean on Europa. Furthermore, by understanding the Jupiter system and unraveling the history of its evolution from initial formation to the emergence of possible habitats and life, gives insight into how giant planets and their satellite systems form and evolve. Most important, new light is shed on the potential for the emergence and existence of life in icy satellite oceans. In 2009, NASA released a detailed Jupiter Europa Mission Study (EJSM) that proposed an ambitious Flagship Mission to understand more fully the satellites Europa and Ganymede within the context of the Jovian system. Key to EJSM is the NASA led Jupiter Europa Orbiter (JEO) and the ESA led Jupiter Ganymede Orbiter (JGO). JEO and JGO would execute a choreographed exploration of the Jovian system before settling into orbit around Europa and Ganymede, respectively. The National Academies Planetary Decadal Survey, 2011 has listed the NASA-led JEO as the second highest priority mission for the decade 2013-2022, and if chosen it would be launched in 2020 with arrival at Jupiter in 2025. If the JEO mission is not chosen it is anticipated that there will be opportunities in future decadal cycles. Jupiter Orbit Insertion (JOI) begins a 30-month Jovian system tour followed by nine months of science mapping after Europa Orbit Insertion (EOI) in July 2028. The orbiter will ultimately impact the surface of Europa after the mission is completed. The current JEO mission concept includes a range of instruments on the payload, to monitor dynamic phenomena (such as Io's volcanoes and Jupiters atmosphere), map the Jovian magnetosphere and its interactions with the Galilean satellites, and characterize water oceans beneath the ice shells of Europa and Ganymede. The payload includes a low mass (3.7 Kg) and low power (< 5 W) Thermal Instrument (TI) concept for measuring possible warm thermal anomalies on Europa s cold surface caused by recent (< 10,000 years) eruptive activity. Regions of anomalously high heat flow will be identified by thermal mapping using a nadir pointing, push-broom filter radiometer that provides far-IR imagery in two broad band spectral wavelength regions, 8-20 m and 20-100 m, for surface temperature measurements with better than a 2 K accuracy and a spatial resolution of 250 m/pixel obtained from a 100 Km orbit. The temperature accuracy permits a search for elevated temperatures when combined with albedo information. The spatial resolution is sufficient to resolve Europa's larger cracks and ridge axial valleys. In order to accomplish the thermal mapping, the TI uses sensitive thermopile arrays that are readout by a custom designed low-noise Multi-Channel Digitizer (MCD) ASIC that resides very close to the thermopile linear array outputs. Both the thermopile array and the MCD ASIC will need to show full functionality within the harsh Jovian radiation environment, operating at cryogenic temperatures, typically 150 K to 170 K. In the following, a radiation mitigation strategy together with a low risk Radiation-Hardened-By-Design (RHBD) methodology using commercial foundry processes is given for the design and manufacture of a MCD ASIC that will meet this challenge.

Aslam, Shahid↗