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All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Studies in pulse shape discrimination for an optimized ASIC design

The continued advancements of Silicon Photomultipliers (SiPMs) have made them viable photosensors for low recoil energy Pulse Shape Discrimination (PSD) between fast neutron and gamma interactions when coupled to an appropriate scintillator. At the same time, the large number of channels in a typical array calls for the development of low-cost and low-power electronics. A custom integrated circuit (ASIC) is an ideal solution for this purpose. To assess the requirements for such an ASIC, studies were performed using two scintillators, Stilbene and EJ-276, coupled to a 6 x 6 mm SiPM from Onsemi. We demonstrate that both scintillators are viable for performing PSD for interaction energies from 100 keV to several MeV while optimizing the integration periods used in the PSD metric. These measurements inform the design parameters of the ASIC under development.

Si-PMTs↗
DOE OSTI2024

Performance of a second generation of the Fermilab Constant Fraction Discriminator ASIC for time-stamping long-strip AC-LGAD sensors.

We present the design and performance characterization results of the second generation of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout AC-coupled low gain avalanche detector (AC-LGAD) sensors. This study presents the performance of the ASIC which was optimized specifically for reading out strip AC-LGAD sensors designed for ePIC experiment at EiC. Performance was measured using charge injection and particle beams with prototype AC-LGAD sensors wirebonded to the FCFD ASIC.

Apresyan, A.↗
DOE OSTI2023

A 32-channels readout ASIC for X-ray spectrometry and tracking in the GAPS experiment

Here this work describes the architecture and the experimental results from the characterization of a 32-channels mixed-signal Application-Specific Integrated Circuit (ASIC) developed for the readout of the lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full custom integrated circuit, named SLIDER32 (32-channels Si-LI DEtector Readout) ASIC, has been produced in a commercial 180 nm CMOS technology. The ASIC is comprised of 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit SAR ADC and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

CMS High Granularity Calorimeter ECON-D ASIC overview and radiation testing results

The Compact Muon Solenoid (CMS) Experiment’s High Granularity Calorimeter (HGCAL) upgrade replaces the CMS electromagnetic and hadronic endcap calorimeters in preparation for the high-rate and high-radiation environment of the High Luminosity LHC. To effectively use the over 6 million channels of this highly-segmented “imaging” calorimeter, CMS is pioneering very front-end data compression with the Endcap Concentrator (ECON) ASICs – the ECON-T for the trigger path and the ECON-D for the data path. These 65 nm CMOS ASICs are radiation tolerant (200 Mrad) and low-power (< 2.5 mW/channel). In June 2023, we received the first full-functionality prototype of the data path concentrator ASIC, the ECON-D-P1. This talk will present an overview of the ECON-D-P1, summarize functionality and system testing, and present results from both Total Ionizing Dose (TID) and Single Event Effect (SEE) testing campaigns completed in summer 2023, validating the ECON-D radiation tolerant performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗
DOE OSTI2025

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented in brief. Current documentation is available at https://github.com/SpacelyProject/spacely-docs.

Quinn, Adam [Fermilab]↗
DOE OSTI2026

Two 28-nm front-end ASICs for ultra-fine spatial resolution and precision timing to be 3D integrated with 12 LGADs

The 3DIntSenS Collaboration—a joint effort between SLAC, Fermilab, and LLNL—is developing enabling technologies for next-generation radiation imaging detectors that combine ultra-fine spatial resolution (about 10 µm) with precision timing (<20 ps), while maintaining low power <1 W/cm2 and high data throughput. The approach leverages 3D integration between advanced CMOS readout ASICs and finely pixelated LGAD sensors to achieve the performance and scalability required for large-area, high-rate applications. High-granularity, precision-timing detectors are essential for scientific advances in HEP, NP, BES, and FES, but widespread adoption is limited by the cost and complexity of 3D integration. To close this gap, the collaboration is developing LGAD sensors compatible with 12-inch commercial CMOS processes, enabling cost-effective integration with high-performance ASICs under development. We present two 28 nm CMOS ASIC prototypes, including a low-jitter front end, and in-pixel TDC demonstrating sub-10 ps timing resolution. These advances represent a critical step toward scalable, high-resolution radiation imaging systems for future scientific instrumentation.

England, Troy [Fermilab] (ORCID:0000000154405255)↗
DOE OSTI2026

Two 28-nm front-end ASICs for ultra-fine spatial resolution and precision timing to be 3D integrated with 12 LGADs

The 3DIntSenS Collaboration—a joint effort between SLAC, Fermilab, and LLNL—is developing enabling technologies for next-generation radiation imaging detectors that combine ultra-fine spatial resolution (about 10 µm) with precision timing (<20 ps), while maintaining low power <1 W/cm2 and high data throughput. The approach leverages 3D integration between advanced CMOS readout ASICs and finely pixelated LGAD sensors to achieve the performance and scalability required for large-area, high-rate applications. High-granularity, precision-timing detectors are essential for scientific advances in HEP, NP, BES, and FES, but widespread adoption is limited by the cost and complexity of 3D integration. To close this gap, the collaboration is developing LGAD sensors compatible with 12-inch commercial CMOS processes, enabling cost-effective integration with high-performance ASICs under development. We present two 28 nm CMOS ASIC prototypes, including a low-jitter front end, and in-pixel TDC demonstrating sub-10 ps timing resolution. These advances represent a critical step toward scalable, high-resolution radiation imaging systems for future scientific instrumentation.

England, Troy [Fermilab] (ORCID:0000000154405255)↗
DOE OSTI2026

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences↗
DOE OSTI2024

Reusable Verification Components for High-Energy Physics readout ASICs

Verification is a critical aspect of designing front-end (FE) readout ASICs for High-Energy Physics (HEP) experiments. These ASICs share several similar functional features, resulting in similar verification objectives, which can be addressed using comparable verification strategies. This contribution presents a set of re-usable verification components for addressing common verification tasks, such as clock generation, reset handling, configuration, as well as hit and fault injections. The components were developed as part of the CHIPS initiative and they have been successfully used in the verification of multiple HEP ASICs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Optimization and Performance Characterization of the Second Generation Fermilab Constant Fraction Discriminator Readout ASIC

We present the optimization and performance characterization of the second-generation Fermilab Constant Fraction Discriminator ASIC (FCFD), designed for the readout of AC-coupled low-gain avalanche detector (LGAD) strip-sensors. The FCFD is explicitly engineered to be insensitive to signal-amplitude variations, thereby removing the need for time-walk correction that is required in other LGAD time-stamping readout ASICs. This updated version, referred to as FCFD1.1, incorporates several enhancements over the first iteration to address key challenges in AC-coupled LGAD front-end design. We outline the primary readout-ASIC design considerations for these applications, describe the methodology used to evaluate critical sensor and system parameters, and summarize the additionally implemented features. Performance measurements using injected charge signals and minimum-ionizing particles in test-beams demonstrate a time resolution of approximately 40 ps and a position resolution of roughly \SI{15}{\micro\meter} when tested with beam particles uniformly over the active area of the sensor.

Apresyan, Artur [Fermilab] (ORCID:0000000261860130↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
DOE OSTI2020

Design of a Time-to-Digital Converter ASIC and a mini-DAQ system for the Phase-2 upgrade of the ATLAS Monitored Drift Tube detector

We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been implemented for the configuration and flow control logic. Here, the total power consumption is increased by less than 10 mW while achieving the same time resolution and channel uniformity. A mini-DAQ system has been built to verify the front-end electronics chain with the new prototype together with other ASICs and boards in triggered mode. Cosmic ray tests with a small-diameter MDT chamber indicate that the configuration and data transmission of the readout electronics perform well. It is expected that this prototype design will be used in the final production.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Design and Challenges of Edge Computing ASICs on Front-End Electronics

In situ or hardware-embedded data processing of raw signals, close to their source, in radiation detectors is expected to provide dramatic improvements in data quality and volumes. However, the implementation of artificial neural networks (ANNs) in the front-end electronics, and the design of custom integrated circuits (ASICs), comes with challenges. In addition, detectors have to operate with limited power budget and implement complex functionalities in a very dense space. They often are exposed to extreme conditions as they work in high-radiation environments and/or cryogenic temperatures. This paper presents examples of applications and design methodologies for in-situ ANNs, along with the challenges of retaining the fidelity of the trained networks. For illustration, we use the problem of estimating the energy deposited by the radiation from digitized waveforms. The proposed implementation starts with an ML algorithm trained in Qkeras and eventually leads to an equivalent ASIC implementation. The associated design challenges in realizing energy and area efficient implementations in CMOS processes are reviewed. Novel approaches that employ hybrid technologies (combination of CMOS with memristors), in-memory computing models, and bio-inspired spiking neural networks are also highlighted

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network (NN) autoencoder model can be implemented in a radiation-tolerant application-specific integrated circuit (ASIC) to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the Compact Muon Solenoid (CMS) experiment at the CERN Large Hadron Collider. The advantage of the machine learning approach is in the flexibility and configurability of the algorithm. By changing the NN weights, a unique data compression algorithm can be deployed for each sensor in different detector regions and changing detector or collider conditions. To meet area, performance, and power constraints, we perform quantization-aware training to create an optimized NN hardware implementation. The design is achieved through the use of high-level synthesis tools and the hls4ml framework and was processed through synthesis and physical layout flows based on a low-power (LP)-CMOS 65-nm technology node. The flow anticipates 200 Mrad of ionizing radiation to select gates and reports a total area of 3.6 mm 2 and consumes 95 mW of power. The simulated energy consumption per inference is 2.4 nJ. Furthermore, this is the first radiation-tolerant on-detector ASIC implementation of an NN that has been designed for particle physics applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Characterization of the First Prototype of the L1K65n Differential-Output Charge-Sensitive Preamplifier ASIC for High-Performance, Low-Background HPGe Detector Readout

Next-generation neutrinoless double-beta (0νββ) decay searches require a large detector/isotope mass and very low radioactive backgrounds. The upcoming LEGEND-1000 experiment (Large Enriched Germanium Experiment for Neutrinoless double-beta Decay) constitute a ton-scale array of several hundred high-purity germanium (HPGe) detectors enriched in 76Ge, the isotope of interest. It aims to reach a sensitivity beyond 10 28 years on the 0νββ decay half-life of 76Ge, necessitating an order of magnitude reduction in background with respect to the state of the art. This will require the implementation of a dedicated application specific integrated circuit (ASIC) preamplifier that will significantly lower background contribution compared to the conventional low-mass front end (LMFE) employed in the Majorana Demonstrator and LEGEND-200 experiments while maintaining or improving energy resolution and other performance parameters. Features include a high (9 MeV) dynamic range with noise low enough to achieve a trigger threshold of <1 keV, a single power supply to reduce background-inducing cabling, and a differential output to maintain signal integrity over several meters of transmission line. The chip would be optimized to operate in liquid argon (87 K) and be able to do so reliably for ten years. Following on from an earlier 180-nm prototype, we have developed a differential-output charge-sensitive preamplifier ASIC fabricated in a 65-nm process, 1×2 mm in size, that addresses these needs. Here, we present recent results from the successful testing and characterization of the first version of this device.

ASIC↗
DOE OSTI2020

Investigation of ASIC-based signal readout electronics for LEGEND-1000

LEGEND, the Large Enriched Germanium Experiment for Neutrinoless ββ Decay, is a ton-scale experimental program to search for neutrinoless double beta (0νββ) decay in the isotope 76 Ge with an unprecedented sensitivity. Building on the success of the low-background 76 Ge-based GERDA and Majorana Demonstrator experiments, the LEGEND collaboration is targeting a signal discovery sensitivity beyond 10 28 yr on the decay half-life with approximately 10 t∙yr of exposure. Signal readout electronics in close proximity to the detectors plays a major role in maximizing the experiment's discovery sensitivity by reducing electronic noise and improving pulse shape analysis capabilities for the rejection of backgrounds. However, the proximity also poses unique challenges for the radiopurity of the electronics. Application-specific integrated circuit (ASIC) technology allows the implementation of the entire charge sensitive amplifier (CSA) into a single low-mass chip while improving the electronic noise and reducing the power consumption. In this work, we investigated the properties and electronic performance of a commercially available ASIC CSA, the XGLab CUBE preamplifier, together with a p-type point contact high-purity germanium detector. We show that low noise levels and excellent energy resolutions can be obtained with this readout. Moreover, we demonstrate the viability of pulse shape discrimination techniques for reducing background events.

47 OTHER INSTRUMENTATION↗