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A Zero Bouncing Circuit for Battery Short-Circuit Model Development.
Abstract not provided.
Dimming LED circuit augmenting DC/DC controller integrated circuit
Embodiments include systems, methods, and apparatuses for providing a dimming function in a single stage AC input light emitting diode (LED) driver with a controller that contains an on-chip error amplifier and an on-chip fixed reference voltage source coupled to a first input of the error amplifier. The controller controls a duty cycle of a switching transistor to cause a feedback voltage, applied to a first package input terminal, to match the reference voltage. To achieve a dimming function, a voltage across a current sense resistor in series with the LEDs is applied to a first input of a high gain differential amplifier, and a variable dimming control voltage is applied to a second input of the differential amplifier. The output of the differential amplifier is coupled to the first package input terminal. The differential amplifier input signals will be matched at the target LED current level.
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning
Unlike circuit parameter and sizing optimizations, the automated design of analog circuit topologies poses significant challenges for learning-based approaches. One challenge arises from the combinatorial growth of the topology space with circuit size, which limits the topology optimization efficiency. Moreover, traditional circuit evaluation methods are time-consuming, while the presence of data discontinuity in the topology space makes the accurate prediction of circuit performance exceptionally difficult for unseen topologies. To tackle these challenges, we design a novel Graph-Transformer-based Network (GTN) as the surrogate model for circuit evaluation, offering a substantial acceleration in the speed of circuit topology optimization without sacrificing performance. Our GTN model architecture is designed to embed voltage changes in circuit loops and current flows in connected devices, enabling accurate performance predictions for circuits with unseen topologies. To address the cold start problem when scaling GTN to large-scale circuits, we further introduce a curriculum learning strategy that progressively trains GTN from small-scale to large-scale circuits. This approach enables the model to first learn fundamental physical principles from simpler topologies and gradually adapt to complex configurations, effectively bridging the circuit complexity gap and improving prediction accuracy. Taking the power converter circuit design as an experimental task, our GTN model significantly outperforms an analytical approach and baseline methods directly utilizing graph neural networks. Furthermore, GTN achieves less than 5% relative error and 196× speed-up compared with high-fidelity simulation. Notably, our GTN surrogate model empowers an automatic circuit design framework to discover circuits of comparable quality to those identified through high-fidelity simulation while reducing the time required by up to 98.2%. With curriculum learning, the enhanced GTN achieves a 51% improvement for performance prediction of large-scale circuits compared to the GTN model without this strategy. These advancements establish GTN as a scalable framework for automated analog circuit design across varying circuit complexity levels.
Reoptimization of Quantum Circuits via Hierarchical Synthesis
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block opti-mization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noisy simulations, and large-size circuits on analytical models. Our technique can be applied after existing optimizations to achieve higher circuit fidelity. Further, using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compiler optimizations such as t|ket). When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits, Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation tool chain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains to further improve the circuit fidelity.
A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning
Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.
Pilot-Scale Testing of an Integrated Circuit for the Extraction of Rare Earth Minerals and Elements from Coal and Coal Byproducts Using Advanced Separation Technologies
The primary objective of this project was to develop and demonstrate an integrated pilot-scale circuitry for recovering high-value rare earth elements (REEs) from coal and coal byproducts. The target performance was to produce a mixed REE product with content of at least two percent by weight on a dry mass basis in a cost-effective and environmentally benign manner. During the first nine months of the project period (Phase 2 Budget Period 2), pilot plant construction was completed including all field site startup activities such as permitting, engineering design, procurement/bidding, unit fabrication, site construction, equipment installation, module assembly, safety training, and circuit shakedown. During the remaining 21 months of project period (Phase 2 Budget Period 3), detailed field-testing activities were performed including feedstock sample collection and preparation, exploratory testing, circuit modification, detailed parametric study, and performance optimization. A detailed techno-economic analysis was performed based on the pilot plant testing findings which provided various scenarios for REE production. The project successfully accomplished the proposed target performance by producing mixed rare earth oxide (REO) with greater than 90% purity by weight in a continuous pilot scale operation from two distinctly different coarse refuse materials (i.e., West Kentucky No. 13 and Fire Clay coal seams), and at least three secondary sources (i.e., heap leach process and naturally formed acid mine drainage system). Project partners included the University of Kentucky, Virginia Tech, West Virginia University, Alliance Coal, Blackhawk Mining, Mineral Refining Company, and Mineral Separation Technologies. The pilot scale test facility was constructed at a former mining complex owned by Alliance Natural Resource Partners (Alliance Coal). The site was rehabilitated to accommodate the equipment installation, construction and fabrication, electrical power requirement, water line management and containment. The process units constructed and installed included X-ray sorting unit, crushing and grinding unit, physical separation unit, acid leaching unit, solvent extraction unit, and wastewater management unit. A rare earth mineral concentration unit was constructed as a standalone unit for flexible operation. A detailed environmental assessment and control plan was carried out to identify and quantify any potential impacts of the pilot-scale processing circuitry on the human and eco-system health and well-being. Corresponding mitigation strategies and control measures were provided. A conceptual flowsheet was developed to effectively remove thorium and uranium from high purity rare earth oxide mix or any potential radionuclide enriched stream. The two distinct feedstock materials were secured from the Blackhawk Mining Complex in eastern Kentucky where the Fire Clay (Hazard No. 4) seam is processed. The West Kentucky No. 13 (Baker) coarse refuse material was collected from an active process stream at an Alliance coal preparation plant located in western Kentucky. Characterization analysis indicated that both of feed materials generated from the two sources contained >300 ppm of TREEs on a dry whole mass basis which met the requirements for a qualified feed stock. The two feedstocks were further upgraded using a dual x-ray sorter to prepare the feed material for hydrometallurgical circuit. Thermal treatment on feed material prior to leaching was found to: 1) improve the leaching recovery of REEs, 2) increase the leaching kinetics, and 3) allow the leaching reaction to occur at lower acidity. Roasting at 600°C was selected as the pre-treatment condition for both West Kentucky No. 13 and Fire Clay coarse refuse material. Over 40% of leaching recovery was achieved by roasting West Kentucky No. 13 material having a top particle size of 3 mm in the pilot scale operation using 1.2M sulfuric acid leaching at 75OC. Initial pilot scale testing involved continuous operation of the pilot plant for 94 hours. The leaching unit was operated at solid-to-liquid ratio of 1 to 10 (w/v) using 0.5M sulfuric acid solution at a temperature of 75°C. The continuous solvent extraction circuit utilized rougher and cleaner units with DEHPA and TBP as the extractants. An innovative stripping circuit was developed to accumulate the REE concentration in the stripping solution to a level above 600 ppm. A bleed stream from the recycled strip solution was treated using oxalic acid precipitation which produced a high grade rare earth oxalate. The oxalate product was roasted to remove the oxalate which produced a rare earth oxide product having a purity greater 90%. Due to high concentrations of contaminant ions in the pregnant leach solution (PLS), a modified flowsheet was developed that involved pre-concentration of the REEs using multiple stages of precipitation and redissolution. The advantage of this process was improved removal of contamination before the downstream purification process and a significant cost reduction relative to the circuit that utilized the solvent extraction process. The modified circuitry included processes involving leaching, multistage precipitation, redissolution, and oxalate precipitation followed by roasting of the oxalate product. The circuit produced a mixed REO that was 92.96% pure from the initial test. A detailed parametric test plan was carried out which involved varying key parameters including solids feed rate, acid flowrate, acid concentration, multistage precipitation pH, redissolution pH, oxalate precipitation dosage and pH. The response variables included REE recovery, contaminant recovery, REO product grade and overall chemical consumption. Test results indicated that the acid-to-solid ratio is the key parameter to leaching efficiency as performance deteriorated with an increase in solids concentration. The optimal pH determined for REE precipitation and redissolution was 6.5 and 2.5, respectively. Additional tests were conducted to further improve the flowsheet. Recirculating a portion of the PLS to the feed of the leach tanks improved the leaching performance by lowering the pH of the leaching system and reducing the contamination recovery by shortening the residence time. Moreover, the removal of Al prior to REE precipitation significantly reduced the oxalic acid consumption in the oxalate precipitation circuit. The modified circuit produced over 90% grade REO by weight from both West Kentucky No. 13 and Fire Clay coarse refuse material in pilot scale continuous test programs. A case analysis model was developed to project the REE and major contaminants concentration in each PLS stream based on the leaching condition, pH cut point, and oxalic acid dosage. A correlation was established using empirical and semi-empirical models. Using the models, chemical consumption required for each stage was predicted based on the projected performance of the hydrometallurgy circuit. After identifying the optimum conditions, validation tests were carried out for the treatment of both West Kentucky No. 13 and Fire Clay coarse refuse materials in the pilot plant. The actual circuit performance and chemical consumptions were very close to the model predictions. Other than the two coarse refuse sources, several secondary feedstocks were also tested in the pilot plant facility. A “heap leach” system was constructed using the coarse refuse material generated from cleaning the West Kentucky No. 13 seam coal. Using the two stage SX rougher and cleaner circuit, a concentrate with a grade >90% REO was produced while recovering >97% of the REEs from the heap leach PLS. Naturally generated acid mine drainage (AMD) from West Kentucky No.13 mine was processed using the multistage precipitation circuit in the pilot plant in a test conducted for a period of 32 hours. The final grade of the mix RE oxide produced from the AMD was 90.84% with an overall circuit recovery of 64%. The primary source of REE was the selective precipitation steps involving iron and aluminum rejection. The hydrophobic-hydrophilic separation (HHS) process was proven to effectively recover coal from fine waste materials. For REM recovery, the HHS process was able to produce concentrates at grades of approximately 1.8% REE on an ash basis; however, recovery values were typically low, <10%, under the optimal conditions determined in the laboratory-scale testing. Staged testing of the pilot-scale HHS process for coal recovery and semi-continuous laboratory testing for REM testing showed that a total concentration ratio of more than 15x was observed for the REM recovery process. A circuit simulation package was developed for REE extraction and purification using a spreadsheet-based platform (Microsoft Excel). The REESim circuit simulation package is configured to track the mass and volume flows of components passing through a series of unit operations specified and configured by the user. The mass rates can then be utilized by the user to determine important performance indicators such as product mass yields, concentrate purity levels, element-by-element recoveries, and so forth. The techno-economic analysis showed that the roasting and leaching operations were the most expensive capital items, each contributing approximately 30% to the total capital cost. One notable contributor to the high production costs was the low REE recovery observed in the pilot scale trials. The product basket price was shown to have a strong influence on the economic viability of the scenarios, with the scandium price being the most significant influencer. Operating cost was shown to be extremely sensitive to REE recovery, REE feed grade, and leaching acid consumption. An analysis of ten different scenarios for a 500 t/h commercial operation revealed that three were economically favorable, producing internal rates of return varying from 27.7% to 33.1% and payback periods of 4 to 5 years. The project successfully developed and demonstrated a process to recover REEs from coal and coal byproducts in a pilot-plant operation which consistently produced over 90% grade REO mix from varies types of feedstocks. Commercialization analysis showed that the technology readiness level successfully achieved TRL 6 at the end of the project and demonstrated the need and the potential for scaling the process to further advance the technologies toward the goal of providing a domestic supply of REEs at a commercial scale.
Quantum circuit cutting with maximum-likelihood tomography
Abstract We introduce maximum-likelihood fragment tomography (MLFT) as an improved circuit cutting technique for running clustered quantum circuits on quantum devices with a limited number of qubits. In addition to minimizing the classical computing overhead of circuit cutting methods, MLFT finds the most likely probability distribution for the output of a quantum circuit, given the measurement data obtained from the circuit’s fragments. We demonstrate the benefits of MLFT for accurately estimating the output of a fragmented quantum circuit with numerical experiments on random unitary circuits. Finally, we show that circuit cutting can estimate the output of a clustered circuit with higher fidelity than full circuit execution, thereby motivating the use of circuit cutting as a standard tool for running clustered circuits on quantum hardware.
Circuit complexity and functionality: A statistical thermodynamics perspective
Circuit complexity, defined as the minimum circuit size required for implementing a particular Boolean computation, is a foundational concept in computer science. Determining circuit complexity is believed to be a hard computational problem. Recently, in the context of black holes, circuit complexity has been promoted to a physical property, wherein the growth of complexity is reflected in the time evolution of the Einstein-Rosen bridge (“wormhole”) connecting the two sides of an anti-de Sitter “eternal” black hole. Here, we are motivated by an independent set of considerations and explore links between complexity and thermodynamics for functionally equivalent circuits, making the physics-inspired approach relevant to real computational problems, for which functionality is the key element of interest. In particular, our thermodynamic framework provides an alternative perspective on the obfuscation of programs of arbitrary length—an important problem in cryptography—as thermalization through recursive mixing of neighboring sections of a circuit, which can be viewed as the mixing of two containers with “gases of gates.” This recursive process equilibrates the average complexity and leads to the saturation of the circuit entropy, while preserving functionality of the overall circuit. The thermodynamic arguments hinge on ergodicity in the space of circuits which we conjecture is limited to disconnected ergodic sectors due to fragmentation. The notion of fragmentation has important implications for the problem of circuit obfuscation as it implies that there are circuits of same size and functionality that cannot be connected via a polynomial number of local moves. Furthermore, we argue that fragmentation is unavoidable unless the complexity classes NP and coNP coincide, a statement that implies the collapse of the polynomial hierarchy of computational complexity theory to its first level.
A review of crosstalk polymorphic circuits and their scalability
Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.
Characterizing the Reproducibility of Noisy Quantum Circuits
The ability of a quantum computer to reproduce or replicate the results of a quantum circuit is a key concern for verifying and validating applications of quantum computing. Statistical variations in circuit outcomes that arise from ill-characterized fluctuations in device noise may lead to computational errors and irreproducible results. While device characterization offers a direct assessment of noise, an outstanding concern is how such metrics bound the reproducibility of a given quantum circuit. Here, we first directly assess the reproducibility of a noisy quantum circuit, in terms of the Hellinger distance between the computational results, and then we show that device characterization offers an analytic bound on the observed variability. We validate the method using an ensemble of single qubit test circuits, executed on a superconducting transmon processor with well-characterized readout and gate error rates. The resulting description for circuit reproducibility, in terms of a composite device parameter, is confirmed to define an upper bound on the observed Hellinger distance, across the variable test circuits. This predictive correlation between circuit outcomes and device characterization offers an efficient method for assessing the reproducibility of noisy quantum circuits.
Power supply circuit with multiple stages for converting high voltage to low voltage and power train having the same
A power supply circuit for converting a first voltage to a second voltage where the first voltage is greater than the second voltage, and a power train having the same, are provided. The power supply circuit may have multiple stages and each stage of the power supply circuit may include a first circuit block configured to provide a start-up power to a second circuit block; a second circuit block configured to generate a Pulse-Width-Modulation (PWM) signal that controls a pulse duration of a transistor; a third circuit block configured to activate or deactivate the transistor based on the PWM signal; a fourth circuit block configured to reset a magnetic flux in a transformer to a zero state when the transistor is deactivated; and a fifth circuit block configured to maintain an output of a stage below a predetermined value by adjusting a voltage across the transformer.
Direct current momentary circuit interrupter
A momentary circuit interrupter in series connection with a mechanical switch to provide protection against short circuit faults in a DC power circuit. The momentary circuit interrupter injects a transient voltage pulse via a pulse transformer to reduce a DC fault current to near zero in a DC circuit branch, thus allowing the mechanical switch to disconnect the faulty branch under a near zero-current condition. The power electronic circuit on the primary side of the transformer controls the discharge of a plurality of pre-charged capacitors to generate the transient voltage pulse during the fault interruption process, but otherwise does not incur any power loss during normal operation. The secondary winding of the pulse transformer conducts the main DC current, and is highly conductive to minimize the conduction power loss. The invention provides ultrafast response to a short circuit fault (even faster than solid-state circuit breakers and much faster than hybrid circuit breakers), significantly reduced overcurrent stress in the power system, and/or ultralow conduction power losses.
Quantum circuit fidelity estimation using machine learning
The computational power of real-world quantum computers is limited by errors. When using quantum computers to perform algorithms which cannot be efficiently simulated classically, it is important to quantify the accuracy with which the computation has been performed. In this work, we introduce a machine learning-based technique to estimate the fidelity between the state produced by a noisy quantum circuit and the target state corresponding to ideal noise-free computation. Our machine learning model is trained in a supervised manner, using smaller or simpler circuits for which the fidelity can be estimated using other techniques like direct fidelity estimation and quantum state tomography. Here we demonstrate that, for simulated random quantum circuits with a realistic noise model, the trained model can predict the fidelities of more complicated circuits for which such methods are infeasible. In particular, we show that the trained model may make predictions for circuits with higher degrees of entanglement than were available in the training set and that the model may make predictions for non-Clifford circuits even when the training set included only Clifford-reducible circuits. This empirical demonstration suggests classical machine learning may be useful for making predictions about beyond-classical quantum circuits for some non-trivial problems.
Model Reduction by Generalized Falk Method for Efficient Field-Circuit Simulations
The Generalized Falk Method (GFM) for coordinate transformation, together with two model-reduction strategies based on this method, are presented for efficient coupled field-circuit simulations. Each model-reduction strategy is based on a decision to retain specific linearly-independent vectors, called trial vectors, to construct a vector basis for coordinate transformation. The reduced-order models are guaranteed to be stable and passive since the GFM is a congruence transformation of originally symmetric positive definite systems. We also show that, unlike the Pad´e-via-Lanczos (PVL) method, the GFM does not generate unstable positive poles while reducing the order of circuit problems. Further, the proposed GFM is also faster when compared to methods of the type Lanczos (or Krylov) that are already widely used in circuit simulations for electrothermal and electromagnetic problems. The concept of response participation factors is introduced for the selection of the trial vectors in the proposed model-reduction methods. Further, we present methods to develop simple equivalent circuit networks for the field component of the overall field-circuit system. The implementation of these equivalent circuit networks in circuit simulators is discussed. With the proposed model-reduction strategies, significant improvement on the efficiency of the generalized Falk method is illustrated for coupled field-circuit problems.
Genetic circuit characterization by inferring RNA polymerase movement and ribosome usage
To perform their computational function, genetic circuits change states through a symphony of genetic parts that turn regulator expression on and off. Debugging is frustrated by an inability to characterize parts in the context of the circuit and identify the origins of failures. Here, we take snapshots of a large genetic circuit in different states: RNA-seq is used to visualize circuit function as a changing pattern of RNA polymerase (RNAP) flux along the DNA. Together with ribosome profiling, all 54 genetic parts (promoters, ribozymes, RBSs, terminators) are parameterized and used to inform a mathematical model that can predict circuit performance, dynamics, and robustness. The circuit behaves as designed; however, it is riddled with genetic errors, including cryptic sense/antisense promoters and translation, attenuation, incorrect start codons, and a failed gate. While not impacting the expected Boolean logic, they reduce the prediction accuracy and could lead to failures when the parts are used in other designs. Finally, the cellular power (RNAP and ribosome usage) required to maintain a circuit state is calculated. This work demonstrates the use of a small number of measurements to fully parameterize a regulatory circuit and quantify its impact on host.