SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Language problem areas are summarized and possible solutions are discussed. Areas covered are: (1) double complex, (2) arrays of work space in library subroutines, (3) calls from a library subprogram to user code, (4) decomposition and synthesis of floating-point numbers, (5) environment parameters, (6) precision function, and (7) control structures.
The UNIX operating system supports a number of software tools; a mathematical equation-setting language, a phototypesetting language, a FORTRAN preprocessor language, a text editor, and a command interpreter. The design, implementation, documentation, and maintenance of a portable FORTRAN test of the floating-point arithmetic unit of a computer is used to illustrate these tools at work.
The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16,384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.
Numerical weather prediction models, which involve the solution of non-linear partial differential equations at points on an extensive three dimensional grid, are ideally suited for processing on vector machines. It was logical therefore that the new global forecast model to be implemented at the Meteorological Office should be written in vector code for the CYBER 205. In order to achieve full efficiency and to reduce storage requirements the model used 32-bit arithmetic which was found to provide high enough precision. Unfortunately, however, the trigonometrical and logarithmic functions provided by CDC could only handle 64-bit vectors and, although written in efficient scalar code, did not take advantage of the special facilities of a vector processor. It was therefore necessary to rewrite the functions in vector code to handle both 32 and 64-bit vectors. There was also no half-precision compiler available for the Cyber 205 at that time and so the functions, like the model, had to make extensive use of the special call syntax. This made the code more difficult to write but it allowed much greater flexibility in that it became possible to access the exponent of a floating-point number independently of its coefficient. A description is given of the technique and the results which were achieved are summarized.
Factors motivating the development of computational aerodynamics as a discipline are traced back to the limitations of the tools available to the aerodynamicist before the development of digital computers. Governing equations in exact and approximate forms are discussed together with approaches to their numerical solution. Example results obtained from the successively refined forms of the equations are presented and discussed, both in the context of levels of computer power required and the degree of the effect that their solution has on aerodynamic research and development. Factors pacing advances in computational aerodynamics are identified, including the amount of computational power required to take the next major step in the discipline. Finally, the Numerical Aerodynamic Simulation (NAS) Program - with its 1987 target of achieving a sustained computational rate of 1 billion floating-point operations per second operating on a memory of 240 million words - is briefly discussed in terms of its projected effect on the future of computational aerodynamics.
An approach to modelling the execution time of algorithms on parallel arrays is presented. This time is expressed as a function of the number of processors and system parameters. The resulting model has been applied to a parallel implementation of the conjugate-gradient algorithm on NASA's FEM. Results of experiments performed to compare the model predictions against actual behavior show that the floating-point arithmetic, communication, and synchronization components of the parallel algorithm execution time were correctly modelled. The results also show that the overhead caused by the interaction of the system software and the actual parallel hardware must be reflected in the model parameters. The model has been used to predict the performance of the conjugate gradient algorithm on a given problem as the number of processors and machine characteristics varied.
The results of a numerical experiment on the predictability of terrestrial polar motion using a Bureau International de l'Heure data set from 1967-83 are presented. A floating point predictor was defined by decomposing polar motion into secular motion and annual and Chandler wobbles. The secular term was linear and the others periodic, the former due to atmospheric mass transport and the latter to Eulerian nutation. A least squares estimator was employed with the data base to obtain constants for the model, which is given the name 'floating-point'. A fixed-period predictor was also devised and, in comparison with the floating point predictor in 6 yr estimates of the annual wobble period, failed after a given length of time. It is suggested that the failure is due to atmospheric motions.
Adaptive quantizer for burst-mode synthetic-aperture radar reduces data rate of return signal. Device, called block floating-point quantizer (BFPQ) basically analog-to-digital converter that covers wide dynamic range and discards appropriate lower order bits. BFPQ is, in effect, digital approximator with automatic gain control. Moves floatingpoint marker binary representation of signal data in accordance with perceived dynamic range. Available step sizes thus limited to multiples of underlying smallest quantization step (represented by lowest order bit). Retains only first K most significant bits of signal; (L,K) BFPQ is one that does K-bit quantization of signal originally quantized to L bits. Quantization error simply difference between actual signal level and its binary approximation. Other potential applications for BFPQ include speech compression and picture data compression.
Computers are playing an increasingly important role in the field of aerodynamics such as that they now serve as a major complement to wind tunnels in aerospace research and development. Factors pacing advances in computational aerodynamics are identified, including the amount of computational power required to take the next major step in the discipline. The four main areas of computational aerodynamics research at NASA Ames Research Center which are directed toward extending the state of the art are identified and discussed. Example results obtained from approximate forms of the governing equations are presented and discussed, both in the context of levels of computer power required and the degree to which they either further the frontiers of research or apply to programs of practical importance. Finally, the Numerical Aerodynamic Simulation Program--with its 1988 target of achieving a sustained computational rate of 1 billion floating-point operations per second--is discussed in terms of its goals, status, and its projected effect on the future of computational aerodynamics.
It is often said that the 1980s are becoming the decade of multiinstruction stream or MIMD computers, while the 1970s could be described as the decade of the SIMD (single instruction stream multiple data stream) computers. The availability of microprocessors and VLSI facilities has led to the proposal and construction of novel computer architectures based on linking many hundreds or even thousands of microprocessors, or specially designed VLSI chips. Some of the larger manufacturers offer computers with a small number of CPUs. Because of the variety of the new developments, it was decided to conduct a survey of proposed and existing MIMD computers in the U.S., taking into account a simple classification of the different devices. Particular attention is given to computers which are designed for numerical work with floating-point numbers and the solution of large problems in physics, chemistry, and engineering.
A digital controller was developed using an SKD-51 System Design Kit, which incorporates an 8031 microcontroller. The necessary interfaces were installed in the wire wrap area of the SKD-51 and a pulse width modulator was developed to drive the coil of the actuator. Also, control equations were developed, using floating-point arithmetic. The design of the digital control system is emphasized, and it is shown that, provided certain rules are followed, an adequate design can be achieved. It is recommended that the so-called w-plane design method be used, and that the time elapsed before output of the up-dated coil-force signal be kept as small as possible. However, the cycle time for the controller should be watched carefully, because very small values for this time can lead to digital noise.
The floating-point roundoff error effect under finite word length limitations is analyzed for the time updates of reflection coefficients in the spatial lattice algorithm. It is shown that recursive computation is superior to direct computation under finite word length limitations. Moreover, the forgetting factor, which is conventionally used to smooth the time variations of the inputs, is also a crucial parameter in the consideration of the system stability and adaptability under finite word length constraints.
Scheme devised for asynchronous-message communication system for Mark III hypercube concurrent-processor network. Network consists of up to 1,024 processing elements connected electrically as though were at corners of 10-dimensional cube. Each node contains two Motorola 68020 processors along with Motorola 68881 floating-point processor utilizing up to 4 megabytes of shared dynamic random-access memory. Scheme intended to support applications requiring passage of both polled or solicited and unsolicited messages.
A speech compression project has recently been completed to develop a speech coding algorithm suitable for operation in a mobile satellite environment aimed at providing telephone quality natural speech at 4.8 kbps. The work has resulted in two alternative techniques which achieve reasonably good communications quality at 4.8 kbps while tolerating vehicle noise and rather severe channel impairments. The algorithms are embodied in a compact self-contained prototype consisting of two AT and T 32-bit floating-point DSP32 digital signal processors (DSP). A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. On a wirewrapped card, the prototype's circuit footprint amounts to only 200 sq cm, and consumes about 9 watts of power.
The parallel stratagem in this paper uses scattered square decomposition, introduced by Fox (1985), for its data assignment and then exploits parallelism in the solution steps of the sequential Householder tridiagonalization algorithm. One may condense a real symmetric full matrix A of order n into a tridiagonal form by the stratagem in concurrent machines where N(=D-squared) processors are used. Expressions for efficiency and speedup are given for the evaluation of the stratagem. An alternative stratagem which requires less data transmission but more computations is also discussed. The results shown that the Householder method of tridiagonalization may be implemented on a concurrent machine efficiently by scattered square decomposition provided that the number of matrix elements contained in each processor is much larger than the number of processors of the concurrent machine, and the ratio of the time to transmit one data item from one processor to any other processor to the time to perform a floating-point arithmetic operation is small enough.
VLSI technology is being used to implement a prototype Boolean Vector Machine (BVM), which is a large network of very small processors with equally small memories that operate in SIMD mode; these use bit-serial arithmetic, and communicate via cube-connected cycles network. The BVM's bit-serial arithmetic and the small memories of individual processors are noted to compromise the system's effectiveness in large numerical problem applications. Attention is presently given to the implementation of a basic matrix-vector iteration algorithm for space matrices of the BVM, in order to generate over 1 billion useful floating-point operations/sec for this iteration algorithm. The algorithm is expressed in a novel language designated 'BVM'.
The authors report the final stage of a research project for the NASA mobile satellite experiment (MSAT-X). The work has resulted in two alternative coding techniques which have achieved good communications quality at 4.8 kb/s while tolerating vehicle noise, fading, and a fairly high-error-rate, bursty channel. The authors have constructed a circuit board based on three AT&T 32-bit floating-point DSP32 digital signal processors (DSP) and providing both excess processing power and considerable flexibility for handling different variations of the algorithms. A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. Mounted on a wirewrapped card, the prototype's circuit footprint amounts to only 225 cm2 and consumes about 13 W of power. A description is given of the architecture, signal processing and communication functions, circuitry, and firmware of the prototype. Issues such as synchronization, framing, error control, and modem interface are also addressed.
A brief description is given of the three-frequency polarimetric synthetic-aperture radar built and tested at the Jet Propulsion Laboratory. The radar has the capability to simultaneously acquire fully polarimetric data at P-, L-, and C-bands from a DC-8 airborne platform. The radar has an instantaneous data rate of approximately 2.1 Gb/s and has selectable record rates between 80-240 Mb/s. The system has a wide dynamic range featuring 8-b analog-to-digital converters and full digital floating-point processing. The processing is accomplished offline on a minicomputer system assisted by an array processor. Sample images are presented.