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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

JFET↗
NASA NTRS2015

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗
NASA NTRS2018

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460 °C, ~9.3 MPa (~ 92 Earth atmospheres) chemically reactive environment. Here we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost 3-fold and were accomplished using prototype SiC JFET chips of more than 7-fold increased complexity. The demonstrated advancement marks a significant step towards realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

Integrated Circuit↗
NASA NTRS1996

AlGaN Channel Transistors for Power Management and Distribution

Contained within is the Final report of a Phase 1 SBIR program to develop AlGaN channel junction field effect transistors (JFET). The report summarizes our work to design, deposit, and fabricate JFETS using molecular beam epitaxy growth AlGaN. Nitride growth is described using a RF atomic nitrogen plasma source. Processing steps needed to fabricate the device such as ohmic source-drain contacts, reactive ion etching, gate formation, and air bride fabrication are documented. SEM photographs of fabricated power FETS are shown. Recommendations are made to continue the effort in a Phase 2 Program.

ENERGY MANAGEMENT↗
DOE OSTI2024

ARC-SAFE: Accelerated Response semiconducting Contactors and Surge Attenuation For DC Electrical systems (Final Scientific/Technical Report)

The landscape of power transmission and distribution is quickly evolving as more power conversion is done through power electronics and transmitted or distributed at medium voltage direct current (MVDC). As power electronics tend to store less energy and be less resilient to faults than conventional power transformers, a reliable and fast protection against faults is critical to protect power electronics (PE) based infrastructure, especially for medium- and high-voltage applications. This motivates the development of PE based protection circuits to replace slower contemporary electromechanical breakers. In this project a novel PE based MVDC circuit breaker is developed; the new design is comprised of 1) a normally-on leg made of commercially-available, cascaded SiC junction field effect transistors (JFETs) with a passive balancing network, and 2) a normally-off leg based on an optically-triggered gallium nitride (GaN) photoconductive semiconductor switch (PCSS). The normally-off leg was designed to be quickly turned on, to divert current to an auxiliary dissipative circuit, as the normally-on leg is turned off. This approach, using solid-state devices, was selected for a high-performance, fast-switching operation for the DC circuit breaker as compared to approaches that use slower mechanical switches. To be practical, the circuit breaker must have low conduction loss (low Ron) in the normally-on leg and fast coordinated triggering of the normally-off leg to avoid damage from inductive flyback, which could be considerable for long lengths of cable.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1971

Analog tree-organized multiplexer

An analog tree-organized multiplexer (ATOM) which is intended for use in the telemetry system of an interplanetary spacecraft is designed. The ATOM will be fabricated by a monolithic, dielectric isolation process, and will contain silicon junction field effect transistors (JFET) as the active elements. The effect of the radiation environment on the performance of the ATOM is analyzed. The result indicates that the expected radiation environment will cause only minor changes in the preradiation characteristics of ATOM. The JFET in the ATOM is designed to meet the electrical requirements when fabricated by either the double poly-dielectric isolation process or the raised dielectric isolation process. The effect of the heat treatment required for the dielectric isolation process on the diffusion profile of the JFET is described. The layout of the ATOM circuit for fabrication by either the double poly or raised dielectric isolation process is also given.

Crabbe, J. S.↗
NASA NTRS1981

High sensitivity operation of discrete solid state detectors of 4 K

Techniques are described to allow operation of discrete solid state detectors at 4 K with optimized junction field effect transistor (JFET) amplifiers. Three detector types cover the 0.6-4 micron spectral range with a noise equivalent power (NEP) of approximately 10 to the -16th per sq rt Hz for two of the types and potential improvement to this performance for the third. Lower NEPs can be anticipated at longer IR wavelengths.

Rieke, G. H.↗
NASA NTRS1984

Advanced components for spaceborne infrared astronomy

The need for improved cryogenic components to be used in future spaceborne infrared astronomy missions was identified. Improved low noise cryogenic amplifiers operated with infrared detectors, and better cryogenic actuators and motors with extremely low power dissipation are needed. The feasibility of achieving technological breakthroughs in both of these areas was studied. An improved silicon junction field effect transistor (JFET) could be developed if: (1) high purity silicon; (2) optimum dopants; and (3) very high doping levels are used. The feasibility of a simple stepper motor equipped with superconducting coils is demonstrated by construction of such a device based on a standard commercial motor. It is found that useful levels of torque at immeasurably low power levels were achieved. It is concluded that with modest development and optimization efforts, significant performance gains is possible for both cryogenic preamplifiers and superconducting motors and actuators.

Davidson, A. W.↗
NASA NTRS1983

Long wavelength photoconductive detectors for airborne and orbital infrared astronomy

Seven gallium doped germanium (Ge:Ga) photoconductive infrared detectors were fabricated and mounted in integrating cavities. In addition, a cold preamplifier package consisting of J230 junction field effect transistors (JFETs) was produced. Tests of the system under low photon background conditions indicated that sensitivity was limited by the Johnson noise of the load resistor. The detectors were mounted in the Ames cooled grating spectrometer, and flown on the Kuiper Airborne Observatory. Good quality astronomical data were obtained during the flight of 7 July 1983.

Houck, J. R.↗
NASA NTRS1984

Cryogenic telescope on the Infrared Astronomical Satellite (IRAS)

The Infrared Astronomical Satellite (IRAS) has completed an unbiased all-sky survey at wavelengths from 10 to 100 microns. The design and performance of the focal plane array is described with emphasis on in-orbit measurements of the sensitivity and stability. In the four broad spectral bands centered at 12, 25, 60, and 100 microns, the system noise equivalent flux density (NEFD) values are in Jy/(Square root of Hz), 0.03, 0.025, 0.046, and 0.21, respectively (Jansky = 10 to the -26th W/sq m/Hz). For point sources, a single scan at the survey rate of 3.8 arcmin/s yields limiting flux densities at the 3-sigma confidence level of 0.36, 0.30, 0.39, and 1.2 Jy. The dc stability of the junction field effect transistor (JFET) amplifiers and the excellent off-axis rejection of the telescope permit total flux measurements of extended infrared emission at levels below 6,000,000 Jy/sr. Response of the extrinsic silicon and germanium photo-detectors to ionizing radiation is described.

Low, F. J.↗
NASA NTRS2000

Characteristics of Monolithically Integrated InGaAs Active Pixel Imager Array

Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.

Kim, Q.↗
NASA NTRS2004

A Two-Dimensional, Semiconducting Bolometer Array for HAWC

The Stratospheric Observatory For Infrared Astronomy's (SOFIA's) High resolution Airborne Wideband Camera (HAWC) will use an ion-implanted silicon bolometer array developed at NASA s Goddard Space Flight Center (GSFC). The GSFC Pop-Up Detectors (PUDs) use a unique folding technique to enable a 12 x 32 element closepacked array of bolometers with a filling factor greater than 95%. The HAWC detector uses a resistive metal film on silicon to provide frequency independent, approx. 50% absorption over the 40 - 300 micron band. The silicon bolometers are manufactured in 32-element rows within silicon frames using Micro Electro Mechanical Systems (MEMS) silicon etching techniques. The frames are then cut, "folded", and glued onto a metallized, ceramic, thermal bus "bar". Optical alignment using micrometer jigs ensures their uniformity and correct placement. The rows are then stacked side-by-side to create the final 12 x 32 element array. A kinematic Kevlar suspension system isolates the 200 mK bolometer cold stage from the rest of the 4K detector housing. GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The Junction Field Effect Transistor (JFET) preamplifiers for all the signal channels operate at 120 K, yet they are electrically connected and located in close proximity to the bolometers. The JFET module design provides sufficient thermal isolation and heat sinking for these, so that their heat is not detected by the bolometers. Preliminary engineering results from the flight detector dark test run are expected to be available in July 2004. This paper describes the array assembly and mechanical and thermal design of the HAWC detector and the JFET module.

Voellmer, George M.↗
NASA NTRS2007

Fabrication of a Thermally Isolated and Pre-amplified Transistor Module with Polyimide Micro-wires for Cryogenic Detectors

For use in cryogenic applications such as bolometer and x-ray microcalorimeter arrays, pre-amplifying Junction Field Effect Transistors (JFETs) are often required for the readout electronics. The optimum operating temperature of the JFETs is 130 Kelvin while the cryogenic detectors operate in the milli-Kelvin range. Thus, the JFETs must be heated up but thermally isolated from the surrounding cryogenic instruments. In the past, the thermal isolation was accomplished by suspending the JFETs with low conductance wires such as manganium or stainless steel on a Kevlar support platform [I]. This also achieved electrical connections. However, this assembly required manual soldering work, which could raise a reliability issue for the cryogenic applications. In order to eliminate the manual work, polyimide micro-wires were developed [2]. The wires must be of sufficient length to decrease the heat load and in tension to prevent microphonic noise from vibration of the wires: the polyimide wires were patterned into llS"shaped curves over a thin metal wires such as aluminum, titanium, or niobium. The bilayer of the films were then suspended by etching silicon substrate thus to make freestanding air bridges (enough explanation?). In this paper, we present a method to fabricate micromachined JFET mechanical modules suspended by polyimide Pyraline micro-wires and heated up with built-in aluminum micro-heaters.

Oh, L. H.↗
NASA NTRS2012

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Chen, Liang-Yu↗
NASA NTRS2008

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

Neudeck, Philip G.↗
NASA NTRS2008

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

Neudeck, Philip G.↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

JFET↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Microelectronics↗