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DOE OSTI2025

Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.

Quantum benchmarking↗

NASA NTRS1993

Design and implementation of fuzzy logic controllers

The main objectives of our research are to present a self-contained overview of fuzzy sets and fuzzy logic, develop a methodology for control system design using fuzzy logic controllers, and to design and implement a fuzzy logic controller for a real system. We first present the fundamental concepts of fuzzy sets and fuzzy logic. Fuzzy sets and basic fuzzy operations are defined. In addition, for control systems, it is important to understand the concepts of linguistic values, term sets, fuzzy rule base, inference methods, and defuzzification methods. Second, we introduce a four-step fuzzy logic control system design procedure. The design procedure is illustrated via four examples, showing the capabilities and robustness of fuzzy logic control systems. This is followed by a tuning procedure that we developed from our design experience. Third, we present two Lyapunov based techniques for stability analysis. Finally, we present our design and implementation of a fuzzy logic controller for a linear actuator to be used to control the direction of the Free Flight Rotorcraft Research Vehicle at LaRC.

Abihana, Osama A.↗

NASA NTRS1994

Learning fuzzy logic control system

The performance of the Learning Fuzzy Logic Control System (LFLCS), developed in this thesis, has been evaluated. The Learning Fuzzy Logic Controller (LFLC) learns to control the motor by learning the set of teaching values that are generated by a classical PI controller. It is assumed that the classical PI controller is tuned to minimize the error of a position control system of the D.C. motor. The Learning Fuzzy Logic Controller developed in this thesis is a multi-input single-output network. Training of the Learning Fuzzy Logic Controller is implemented off-line. Upon completion of the training process (using Supervised Learning, and Unsupervised Learning), the LFLC replaces the classical PI controller. In this thesis, a closed loop position control system of a D.C. motor using the LFLC is implemented. The primary focus is on the learning capabilities of the Learning Fuzzy Logic Controller. The learning includes symbolic representation of the Input Linguistic Nodes set and Output Linguistic Notes set. In addition, we investigate the knowledge-based representation for the network. As part of the design process, we implement a digital computer simulation of the LFLCS. The computer simulation program is written in 'C' computer language, and it is implemented in DOS platform. The LFLCS, designed in this thesis, has been developed on a IBM compatible 486-DX2 66 computer. First, the performance of the Learning Fuzzy Logic Controller is evaluated by comparing the angular shaft position of the D.C. motor controlled by a conventional PI controller and that controlled by the LFLC. Second, the symbolic representation of the LFLC and the knowledge-based representation for the network are investigated by observing the parameters of the Fuzzy Logic membership functions and the links at each layer of the LFLC. While there are some limitations of application with this approach, the result of the simulation shows that the LFLC is able to control the angular shaft position of the D.C. motor. Furthermore, the LFLC has better performance in rise time, settling time and steady state error than to the conventional PI controller. This abstract accurately represents the content of the candidate's thesis. I recommend its publication.

Lung, Leung Kam↗

NASA NTRS2005

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

MacLeod, Todd C.↗

NASA NTRS2001

Apparatus for and method of eliminating single event upsets in combinational logic

An apparatus for and method of eliminating single event upsets (or SEU) in combinational logic are used to prevent error propagation as a result of cosmic particle strikes to the combinational logic. The apparatus preferably includes a combinational logic block electrically coupled to a delay element, a latch and an output buffer. In operation, a signal from the combinational logic is electrically coupled to a first input of the latch. In addition, the signal is routed through the delay element to produce a delayed signal. The delayed signal is routed to a second input of the latch. The latch used in the apparatus for preventing SEU preferably includes latch outputs and a feature that the latch outputs will not change state unless both latch inputs are correct. For example, the latch outputs may not change state unless both latch inputs have the same logical state. When a cosmic particle strikes the combinational logic, a transient disturbance with a predetermined length may appear in the signal. However, a function of the delay element is to preferably provide a time delay greater than the length of the transient disturbance. Therefore, the transient disturbance will not reach both latch inputs simultaneously. As a result, the latch outputs will not permanently change state in error due to the transient disturbance. In addition, the output buffer preferably combines the latch outputs in such a way that the correct state is preserved at all times. Thus, combinational logic with protection from SEU is provided.

Gambles, Jody W.↗

DOE OSTI2025

Dynamical logical qubits in the Bacon-Shor code

The Bacon-Shor code is a quantum error correcting subsystem code composed of weight-2 check operators that admits a single logical qubit, and has distance 𝑑 on a 𝑑×𝑑 square lattice. We show that when viewed as a Floquet code, by choosing an appropriate measurement schedule of the check operators, it can additionally host several dynamical logical qubits. Specifically, we identify a period-4 measurement schedule of the check operators that preserves logical information between the instantaneous stabilizer groups. Such a schedule not only measures the usual stabilizers of the Bacon-Shor code, but also measures and promotes gauge operators of the parent subsystem code to additional temporary stabilizers that protect the dynamical logical qubits against errors. We show that the code distance of these Floquet-Bacon-Shor codes scales as Θ⁢(𝑑/√𝑘) on an 𝑛=𝑑×𝑑 lattice with 𝑘 dynamical logical qubits, along with the logical qubit of the parent subsystem code. Unlike the usual Bacon-Shor code, the Floquet-Bacon-Shor code family introduced here can therefore saturate the subsystem bound 𝑘⁢𝑑=𝑂⁡(𝑛). Moreover, several errors are shown to be self-corrected purely by the measurement schedule itself. This work provides insights into the design space for dynamical codes and expands the known approaches for constructing Floquet codes.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2024

StructuredFuzzer: Fuzzing Structured Text-Based Control Logic Applications

Rigorous testing methods are essential for ensuring the security and reliability of industrial controller software. Fuzzing, a technique that automatically discovers software bugs, has also proven effective in finding software vulnerabilities. Unsurprisingly, fuzzing has been applied to a wide range of platforms, including programmable logic controllers (PLCs). However, current approaches, such as coverage-guided evolutionary fuzzing implemented in the popular fuzzer American Fuzzy Lop Plus Plus (AFL++), are often inadequate for finding logical errors and bugs in PLC control logic applications. They primarily target generic programming languages like C/C++, Java, and Python, and do not consider the unique characteristics and behaviors of PLCs, which are often programmed using specialized programming languages like Structured Text (ST). Furthermore, these fuzzers are ill suited to deal with complex input structures encapsulated in ST, as they are not specifically designed to generate appropriate input sequences. This renders the application of traditional fuzzing techniques less efficient on these platforms. To address this issue, this paper presents a fuzzing framework designed explicitly for PLC software to discover logic bugs in applications written in ST specified by the IEC 61131-3 standard. The proposed framework incorporates a custom-tailored PLC runtime and a fuzzer designed for the purpose. We demonstrate its effectiveness by fuzzing a collection of ST programs that were crafted for evaluation purposes. We compare the performance against a popular fuzzer, namely, AFL++. The proposed fuzzing framework demonstrated its capabilities in our experiments, successfully detecting logic bugs in the tested PLC control logic applications written in ST. On average, it was at least 83 times faster than AFL++, and in certain cases, for example, it was more than 23,000 times faster.

47 OTHER INSTRUMENTATION↗

NASA NTRS1974

A motion-constraint logic for moving-base simulators based on variable filter parameters

A motion-constraint logic for moving-base simulators has been developed that is a modification to the linear second-order filters generally employed in conventional constraints. In the modified constraint logic, the filter parameters are not constant but vary with the instantaneous motion-base position to increase the constraint as the system approaches the positional limits. With the modified constraint logic, accelerations larger than originally expected are limited while conventional linear filters would result in automatic shutdown of the motion base. In addition, the modified washout logic has frequency-response characteristics that are an improvement over conventional linear filters with braking for low-frequency pilot inputs. During simulated landing approaches of an externally blown flap short take-off and landing (STOL) transport using decoupled longitudinal controls, the pilots were unable to detect much difference between the modified constraint logic and the logic based on linear filters with braking.

Miller, G. K., Jr.↗

NASA NTRS1988

Specifying real-time systems with interval logic

Pure temporal logic makes no reference to time. An interval temporal logic and an extension to that logic which includes real time constraints are described. The application of this logic by giving a specification for the well-known lift (elevator) example is demonstrated. It is shown how interval logic can be extended to include a notion of process. How the specification language and verification environment of EHDM could be enhanced to support this logic is described. A specification of the alternating bit protocol in this extended version of the specification language of EHDM is given.

Rushby, John↗

NASA NTRS2001

Robust Fault Detection Using Robust Z1 Estimation and Fuzzy Logic

This research considers the application of robust Z(sub 1), estimation in conjunction with fuzzy logic to robust fault detection for an aircraft fight control system. It begins with the development of robust Z(sub 1) estimators based on multiplier theory and then develops a fixed threshold approach to fault detection (FD). It then considers the use of fuzzy logic for robust residual evaluation and FD. Due to modeling errors and unmeasurable disturbances, it is difficult to distinguish between the effects of an actual fault and those caused by uncertainty and disturbance. Hence, it is the aim of a robust FD system to be sensitive to faults while remaining insensitive to uncertainty and disturbances. While fixed thresholds only allow a decision on whether a fault has or has not occurred, it is more valuable to have the residual evaluation lead to a conclusion related to the degree of, or probability of, a fault. Fuzzy logic is a viable means of determining the degree of a fault and allows the introduction of human observations that may not be incorporated in the rigorous threshold theory. Hence, fuzzy logic can provide a more reliable and informative fault detection process. Using an aircraft flight control system, the results of FD using robust Z(sub 1) estimation with a fixed threshold are demonstrated. FD that combines robust Z(sub 1) estimation and fuzzy logic is also demonstrated. It is seen that combining the robust estimator with fuzzy logic proves to be advantageous in increasing the sensitivity to smaller faults while remaining insensitive to uncertainty and disturbances.

Curry, Tramone↗

NASA NTRS2001

Interpreting Abstract Interpretations in Membership Equational Logic

We present a logical framework in which abstract interpretations can be naturally specified and then verified. Our approach is based on membership equational logic which extends equational logics by membership axioms, asserting that a term has a certain sort. We represent an abstract interpretation as a membership equational logic specification, usually as an overloaded order-sorted signature with membership axioms. It turns out that, for any term, its least sort over this specification corresponds to its most concrete abstract value. Maude implements membership equational logic and provides mechanisms to calculate the least sort of a term efficiently. We first show how Maude can be used to get prototyping of abstract interpretations "for free." Building on the meta-logic facilities of Maude, we further develop a tool that automatically checks and abstract interpretation against a set of user-defined properties. This can be used to select an appropriate abstract interpretation, to characterize the specified loss of information during abstraction, and to compare different abstractions with each other.

Fischer, Bernd↗

DOE OSTI2024

Cross-Cap Defects and Fault-Tolerant Logical Gates in the Surface Code and the Honeycomb Floquet Code

We consider the Z 2 toric code, surface code, and Floquet code defined on a nonorientable surface, which can be considered as families of codes extending Shor’s nine-qubit code. We investigate the fault-tolerant logical gates of the Z 2 toric code in this setup, which corresponds to e ↔ m exchanging symmetry of the underlying Z 2 gauge theory. We find that nonorientable geometry provides a new way for the emergent symmetry to act on the code space, and discover the new realization of the fault-tolerant Hadamard gate of the two-dimensional surface code with a single cross cap connecting the vertices nonlocally along a slit, dubbed a nonorientable surface code. This Hadamard gate can be realized by a constant-depth local unitary circuit modulo nonlocality caused by a cross cap. Via folding, the nonorientable surface code can be turned into a bilayer local quantum code, where the folded cross cap is equivalent to a bilayer twist terminated on a gapped boundary and the logical Hadamard only contains local gates with intralayer couplings when being away from the cross cap, as opposed to the interlayer couplings on each site needed in the case of the folded surface code. We further obtain the complete logical Clifford gate set for a stack of nonorientable surface codes and similarly for codes defined on Klein-bottle geometries. We then construct the honeycomb Floquet code in the presence of a single cross cap, and find that the period of the sequential Pauli measurements acts as a H Z logical gate on the single logical qubit, where the cross cap enriches the dynamics compared with the orientable case. We find that the dynamics of the honeycomb Floquet code is precisely described by a condensation operator of the Z 2 gauge theory, and illustrate the exotic dynamics of our code in terms of a condensation operator supported at a nonorientable surface. Published by the American Physical Society 2024

Physics↗

NASA NTRS1973

A m-ary linear feedback shift register with binary logic

A family of m-ary linear feedback shift registers with binary logic is disclosed. Each m-ary linear feedback shift register with binary logic generates a binary representation of a nonbinary recurring sequence, producible with a m-ary linear feedback shift register without binary logic in which m is greater than 2. The state table of a m-ary linear feedback shift register without binary logic, utilizing sum modulo m feedback, is first tubulated for a given initial state. The entries in the state table are coded in binary and the binary entries are used to set the initial states of the stages of a plurality of binary shift registers. A single feedback logic unit is employed which provides a separate feedback binary digit to each binary register as a function of the states of corresponding stages of the binary registers.

Perlman, M.↗

NASA NTRS1974

Four phase logic systems

A four-phase logic system is provided which includes at least four logic networks connected in parallel between a single power line and a reference potential. A four-phase clock generator generates four distinct clock signals from a single-phase clock input at data rate. Each logic network comprises a pair of complementary metal-oxide-semiconductor integrated transistors (CMOST). Each metal-oxide-Semiconductor transistor (MOST) in the pair is responsive to a clock signal which turns the transistor on or off. In each network, there is also at least one MOST which is responsive to a logic signal. The logic transistor is connected in cascade with the pair of CMOSTs.

Petersen, H. L.↗

NASA NTRS1976

Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.

Rickard, D. A.↗

NASA NTRS1983

An interval logic for higher-level temporal reasoning

Prior work explored temporal logics, based on classical modal logics, as a framework for specifying and reasoning about concurrent programs, distributed systems, and communications protocols, and reported on efforts using temporal reasoning primitives to express very high level abstract requirements that a program or system is to satisfy. Based on experience with those primitives, this report describes an Interval Logic that is more suitable for expressing such higher level temporal properties. The report provides a formal semantics for the Interval Logic, and several examples of its use. A description of decision procedures for the logic is also included.

Schwartz, R. L.↗

NASA NTRS1984

Effect of control logic modifications on airstart performance of F100 engine model derivative engines in an F-15 airplane

A series of airstarts were conducted in an F-15 airplane with two prototype Pratt and Whitney F100 Engine Model Derivative engines equipped with Digital Electronic Engine Control (DEEC) systems. The airstart envelope and the time required for airstarts were defined. Comparisons were made between the original airstart logic, and modified logic which was designed to improve the airstart capability. Spooldown airstarts with the modified logic were more successful at lower altitudes than were those with the original logic. Spooldown airstart times ranged from 33 seconds at 250 knots to 83 seconds at 175 knots. The modified logic improved the airstart time from 31% to 53%, with the most improved times at slower airspeeds. Jet fuel starter (JFS)-assisted airstarts were conducted at 7000 m and airstart times were significantly faster than unassisted airstarts. The effect of altitude on airstart times was small.

Crawford, D. B.↗

NASA NTRS1993

Power optimization in logic isomers

Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.

Panwar, Ramesh↗