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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS1972

C-MOS array design techniques: SUMC multiprocessor system study

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

Clapp, W. A.↗
NASA NTRS1991

Formal verification of an MMU and MMU cache

We describe the formal verification of a hardware subsystem consisting of a memory management unit and a cache. These devices are verified independently and then shown to interact correctly when composed. The MMU authorizes memory requests and translates virtual addresses to real addresses. The cache improves performance by maintaining a LRU (least recently used) list from the memory resident segment table.

Schubert, E. T.↗
NASA NTRS1992

Formal mechanization of device interactions with a process algebra

The principle emphasis is to develop a methodology to formally verify correct synchronization communication of devices in a composed hardware system. Previous system integration efforts have focused on vertical integration of one layer on top of another. This task examines 'horizontal' integration of peer devices. To formally reason about communication, we mechanize a process algebra in the Higher Order Logic (HOL) theorem proving system. Using this formalization we show how four types of device interactions can be represented and verified to behave as specified. The report also describes the specification of a system consisting of an AVM-1 microprocessor and a memory management unit which were verified in previous work. A proof of correct communication is presented, and the extensions to the system specification to add a direct memory device are discussed.

Schubert, E. Thomas↗
NASA NTRS1997

Out-of-Core Streamline Visualization on Large Unstructured Meshes

It's advantageous for computational scientists to have the capability to perform interactive visualization on their desktop workstations. For data on large unstructured meshes, this capability is not generally available. In particular, particle tracing on unstructured grids can result in a high percentage of non-contiguous memory accesses and therefore may perform very poorly with virtual memory paging schemes. The alternative of visualizing a lower resolution of the data degrades the original high-resolution calculations. This paper presents an out-of-core approach for interactive streamline construction on large unstructured tetrahedral meshes containing millions of elements. The out-of-core algorithm uses an octree to partition and restructure the raw data into subsets stored into disk files for fast data retrieval. A memory management policy tailored to the streamline calculations is used such that during the streamline construction only a very small amount of data are brought into the main memory on demand. By carefully scheduling computation and data fetching, the overhead of reading data from the disk is significantly reduced and good memory performance results. This out-of-core algorithm makes possible interactive streamline visualization of large unstructured-grid data sets on a single mid-range workstation with relatively low main-memory capacity: 5-20 megabytes. Our test results also show that this approach is much more efficient than relying on virtual memory and operating system's paging algorithms.

Ueng, Shyh-Kuang↗
NASA NTRS1989

Advanced information processing system: Local system services

The Advanced Information Processing System (AIPS) is a multi-computer architecture composed of hardware and software building blocks that can be configured to meet a broad range of application requirements. The hardware building blocks are fault-tolerant, general-purpose computers, fault-and damage-tolerant networks (both computer and input/output), and interfaces between the networks and the computers. The software building blocks are the major software functions: local system services, input/output, system services, inter-computer system services, and the system manager. The foundation of the local system services is an operating system with the functions required for a traditional real-time multi-tasking computer, such as task scheduling, inter-task communication, memory management, interrupt handling, and time maintenance. Resting on this foundation are the redundancy management functions necessary in a redundant computer and the status reporting functions required for an operator interface. The functional requirements, functional design and detailed specifications for all the local system services are documented.

Burkhardt, Laura↗
NASA NTRS2000

JavaGenes and Condor: Cycle-Scavenging Genetic Algorithms

A genetic algorithm code, JavaGenes, was written in Java and used to evolve pharmaceutical drug molecules and digital circuits. JavaGenes was run under the Condor cycle-scavenging batch system managing 100-170 desktop SGI workstations. Genetic algorithms mimic biological evolution by evolving solutions to problems using crossover and mutation. While most genetic algorithms evolve strings or trees, JavaGenes evolves graphs representing (currently) molecules and circuits. Java was chosen as the implementation language because the genetic algorithm requires random splitting and recombining of graphs, a complex data structure manipulation with ample opportunities for memory leaks, loose pointers, out-of-bound indices, and other hard to find bugs. Java garbage-collection memory management, lack of pointer arithmetic, and array-bounds index checking prevents these bugs from occurring, substantially reducing development time. While a run-time performance penalty must be paid, the only unacceptable performance we encountered was using standard Java serialization to checkpoint and restart the code. This was fixed by a two-day implementation of custom checkpointing. JavaGenes is minimally integrated with Condor; in other words, JavaGenes must do its own checkpointing and I/O redirection. A prototype Java-aware version of Condor was developed using standard Java serialization for checkpointing. For the prototype to be useful, standard Java serialization must be significantly optimized. JavaGenes is approximately 8700 lines of code and a few thousand JavaGenes jobs have been run. Most jobs ran for a few days. Results include proof that genetic algorithms can evolve directed and undirected graphs, development of a novel crossover operator for graphs, a paper in the journal Nanotechnology, and another paper in preparation.

Globus, Al↗
NASA NTRS1990

Architecture independent environment for developing engineering software on MIMD computers

Engineers are constantly faced with solving problems of increasing complexity and detail. Multiple Instruction stream Multiple Data stream (MIMD) computers have been developed to overcome the performance limitations of serial computers. The hardware architectures of MIMD computers vary considerably and are much more sophisticated than serial computers. Developing large scale software for a variety of MIMD computers is difficult and expensive. There is a need to provide tools that facilitate programming these machines. First, the issues that must be considered to develop those tools are examined. The two main areas of concern were architecture independence and data management. Architecture independent software facilitates software portability and improves the longevity and utility of the software product. It provides some form of insurance for the investment of time and effort that goes into developing the software. The management of data is a crucial aspect of solving large engineering problems. It must be considered in light of the new hardware organizations that are available. Second, the functional design and implementation of a software environment that facilitates developing architecture independent software for large engineering applications are described. The topics of discussion include: a description of the model that supports the development of architecture independent software; identifying and exploiting concurrency within the application program; data coherence; engineering data base and memory management.

Valimohamed, Karim A.↗
NASA NTRS1997

Application-Controlled Demand Paging for Out-of-Core Visualization

In the area of scientific visualization, input data sets are often very large. In visualization of Computational Fluid Dynamics (CFD) in particular, input data sets today can surpass 100 Gbytes, and are expected to scale with the ability of supercomputers to generate them. Some visualization tools already partition large data sets into segments, and load appropriate segments as they are needed. However, this does not remove the problem for two reasons: 1) there are data sets for which even the individual segments are too large for the largest graphics workstations, 2) many practitioners do not have access to workstations with the memory capacity required to load even a segment, especially since the state-of-the-art visualization tools tend to be developed by researchers with much more powerful machines. When the size of the data that must be accessed is larger than the size of memory, some form of virtual memory is simply required. This may be by segmentation, paging, or by paged segments. In this paper we demonstrate that complete reliance on operating system virtual memory for out-of-core visualization leads to poor performance. We then describe a paged segment system that we have implemented, and explore the principles of memory management that can be employed by the application for out-of-core visualization. We show that application control over some of these can significantly improve performance. We show that sparse traversal can be exploited by loading only those data actually required. We show also that application control over data loading can be exploited by 1) loading data from alternative storage format (in particular 3-dimensional data stored in sub-cubes), 2) controlling the page size. Both of these techniques effectively reduce the total memory required by visualization at run-time. We also describe experiments we have done on remote out-of-core visualization (when pages are read by demand from remote disk) whose results are promising.

Cox, Michael↗
NASA NTRS1991

Performance Analysis of Garbage Collection and Dynamic Reordering in a Lisp System

Generation based garbage collection and dynamic reordering of objects are two techniques for improving the efficiency of memory management in Lisp and similar dynamic language systems. An analysis of the effect of generation configuration is presented, focusing on the effect of a number of generations and generation capabilities. Analytic timing and survival models are used to represent garbage collection runtime and to derive structural results on its behavior. The survival model provides bounds on the age of objects surviving a garbage collection at a particular level. Empirical results show that execution time is most sensitive to the capacity of the youngest generation. A technique called scanning for transport statistics, for evaluating the effectiveness of reordering independent of main memory size, is presented.

Llames, Rene Lim↗
NASA NTRSDate not supplied

BioSentinel: Leading the Way for Deep Space CubeSat Missions

Flagship science missions are not alone in Deep Space thanks to BioSentinel, a 6U spacecraft launched on Artemis-1. BioSentinel is one of the longest operating CubeSats beyond cislunar space. The subsystems and COTS components of the BioSentinel bus are a template for future deep space missions, and the lessons learned from over a year of operations will enable improved performance for the next missions. BioSentinel achieved its unprecedented performance for an SLS secondary payload due to preparation, planning, and a robust design. Pre-launch antenna and interface testing with both DSN and ESA confirmed command and data pathways and allowed for operational flexibility in the critical early hours post-deployment. Mission Operations simulations prior to launch identified potential risks and primed operators to respond in flight, preparing the team to react quickly to successfully detumble the spacecraft and enter a power-positive state. The spacecraft would not have survived without the inclusion of the trailblazing 3D-printed composite cold gas propulsion system. The non-standard tank geometry enabled efficient use of the limited space available in the CubeSat, as well as the capability to detumble the spacecraft and manage momentum, while providing sufficient margin to execute potential delta-V maneuvers. The Iris radio has operated for over 18 months with no significant issues. Initial Iris performance estimates have been accurate throughout the mission. BioSentinel continues to collect data on thermal conditions and to validate our performance models with real-world knowledge. We have received exemplary support from our DSN partners. Following the conclusion of the primary science mission, the Linear Energy Transfer (LET) Spectrometer continued to collect solar and galactic radiation data from its location in heliocentric orbit. The free space dataset offered by the BioSentinel LET is a valuable source of data for model validation and future mission planning. As the spacecraft travels farther from Earth it is poised to provide longitudinally distributed measurements of solar particle events during solar maximum. The lessons learned from BioSentinel suggest key areas to enhance performance. The ability to upload modified flight software can increase the stability of memory management. Additional heaters in the propulsion system design have already proven successful on the Starling mission. Streamlining mission operations can reduce costs, increase data return, and better utilize DSN time. Enhancements such as these will facilitate reliable, long-duration deep space exploration using the proven BioSentinel 6U CubeSat bus.

BioSentinel↗
NASA NTRS1974

Augmented burst-error correction for UNICON laser memory

A single-burst-error correction system is described for data stored in the UNICON laser memory. In the proposed system, a long fire code with code length n greater than 16,768 bits was used as an outer code to augment an existing inner shorter fire code for burst error corrections. The inner fire code is a (80,64) code shortened from the (630,614) code, and it is used to correct a single-burst-error on a per-word basis with burst length b less than or equal to 6. The outer code, with b less than or equal to 12, would be used to correct a single-burst-error on a per-page basis, where a page consists of 512 32-bit words. In the proposed system, the encoding and error detection processes are implemented by hardware. A minicomputer, currently used as a UNICON memory management processor, is used on a time-demanding basis for error correction. Based upon existing error statistics, this combination of an inner code and an outer code would enable the UNICON system to obtain a very low error rate in spite of flaws affecting the recorded data.

Lim, R. S.↗
NASA NTRS1984

A vectorized molecule code

The vectorization of the computational chemistry code, MOLECULE, is discussed. Computational simplifications of molecular integrals, memory management, and contraction schemes are addressed and a brief guide for users is included.

Almloef, J.↗
NASA NTRS1986

Run-time implementation issues for real-time embedded Ada

A motivating factor in the development of Ada as the department of defense standard language was the high cost of embedded system software development. It was with embedded system requirements in mind that many of the features of the language were incorporated. Yet it is the designers of embedded systems that seem to comprise the majority of the Ada community dissatisfied with the language. There are a variety of reasons for this dissatisfaction, but many seem to be related in some way to the Ada run-time support system. Some of the areas in which the inconsistencies were found to have the greatest impact on performance from the standpoint of real-time systems are presented. In particular, a large part of the duties of the tasking supervisor are subject to the design decisions of the implementer. These include scheduling, rendezvous, delay processing, and task activation and termination. Some of the more general issues presented include time and space efficiencies, generic expansions, memory management, pragmas, and tracing features. As validated compilers become available for bare computer targets, it is important for a designer to be aware that, at least for many real-time issues, all validated Ada compilers are not created equal.

Maule, Ruth A.↗
NASA NTRS1989

On the stability of robotic systems with random communication rates

Control problems of sampled data systems which are subject to random sample rate variations and delays are studied. Due to the rapid growth of the use of computers more and more systems are controlled digitally. Complex systems such as space telerobotic systems require the integration of a number of subsystems at different hierarchical levels. While many subsystems may run on a single processor, some subsystems require their own processor or processors. The subsystems are integrated into functioning systems through communications. Communications between processes sharing a single processor are also subject to random delays due to memory management and interrupt latency. Communications between processors involve random delays due to network access and to data collisions. Furthermore, all control processes involve delays due to casual factors in measuring devices and to signal processing. Traditionally, sampling rates are chosen to meet the worst case communication delay. Such a strategy is wasteful as the processors are then idle a great proportion of the time; sample rates are not as high as possible resulting in poor performance or in the over specification of control processors; there is the possibility of missing data no matter how low the sample rate is picked. Asymptotical stability with probability one for randomly sampled multi-dimensional linear systems is studied. A sufficient condition for the stability is obtained. This condition is so simple that it can be applied to practical systems. A design procedure is also shown.

Kobayashi, H.↗
NASA NTRS1992

Parallel simulation today

This paper surveys topics that presently define the state of the art in parallel simulation. Included in the tutorial are discussions on new protocols, mathematical performance analysis, time parallelism, hardware support for parallel simulation, load balancing algorithms, and dynamic memory management for optimistic synchronization.

Nicol, David↗
NASA NTRS1992

Stiffnesses by (TtN) ensemble molecular dynamics

Calculation of elastic constants requires initializing a lattice of atoms, an h matrix defining the computational cell boundaries, and the parameters defining the interatomic potentials, then numerically integrating the equations of motion for the atoms and the computational cell boundaries, calculating strains and stresses at each timestep, and updating at each timestep the average quantities required for calculation of fluctuations. Enforcements of the DYNAMO FORTRAN code included addition of documentation, improved memory management and data flow, and enabling use of several interatomic potentials. Documentation included headers for each subroutine, which document the parameters input to the routine, algorithms employed, and output.

Tibbits, Patrick↗