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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1977

Programmable data communications controller requirements

The design requirements for a Programmable Data Communications Controller (PDCC) that reduces the difficulties in attaching data terminal equipment to a computer are presented. The PDCC is an interface between the computer I/O channel and the bit serial communication lines. Each communication line is supported by a communication port that handles all line control functions and performs most terminal control functions. The port is fabricated on a printed circuit board that plugs into a card chassis, mating with a connector that is joined to all other card stations by a data bus. Ports are individually programmable; each includes a microprocessor, a programmable read-only memory for instruction storage, and a random access memory for data storage.

Source record↗
NASA NTRS1978

A class of programmable satellite receivers

The primary purpose of programmable satellite receivers is to provide flexibility in application through digital control of the important functions of the receiver. This permits the acquisition and demodulation of medium to very low data rates in widely varying communications environments and over a wide range of modulation schemes. The first application of the programmable concept is in the high-reliability, low-power NASA Standard Command Detector Unit. A second programmable receiver has been designed and breadboarded for the Jupiter Orbiter Probe or Galileo mission.

Klare, S. W.↗
NASA NTRS1986

Display system software for the integration of an ADAGE 3000 programmable display generator into the solid modeling package C.A.D. software

A software system that integrates an ADAGE 3000 Programmable Display Generator into a C.A.D. software package known as the Solid Modeling Program is described. The Solid Modeling Program (SMP) is an interactive program that is used to model complex solid object through the composition of primitive geomeentities. In addition, SMP provides extensive facilities for model editing and display. The ADAGE 3000 Programmable Display Generator (PDG) is a color, raster scan, programmable display generator with a 32-bit bit-slice, bipolar microprocessor (BPS). The modularity of the system architecture and the width and speed of the system bus allow for additional co-processors in the system. These co-processors combine to provide efficient operations on and rendering of graphics entities. The resulting software system takes advantage of the graphics capabilities of the PDG in the operation of SMP by distributing its processing modules between the host and the PDG. Initially, the target host computer was a PRIME 850, which was later substituted with a VAX-11/785. Two versions of the software system were developed, a phase 1 and a phase 2. In phase 1, the ADAGE 3000 is used as a frame buffer. In phase II, SMP was functionally partitioned and some of its functions were implemented in the ADAGE 3000 by means of ADAGE's SOLID 3000 software package.

Montoya, R. J.↗
NASA NTRS1988

Implementing neural nets with programmable logic

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Vidal, Jacques J.↗
NASA NTRS1990

Concurrent Image Processing Executive (CIPE). Volume 2: Programmer's guide

This manual is intended as a guide for application programmers using the Concurrent Image Processing Executive (CIPE). CIPE is intended to become the support system software for a prototype high performance science analysis workstation. In its current configuration CIPE utilizes a JPL/Caltech Mark 3fp Hypercube with a Sun-4 host. CIPE's design is capable of incorporating other concurrent architectures as well. CIPE provides a programming environment to applications' programmers to shield them from various user interfaces, file transactions, and architectural complexities. A programmer may choose to write applications to use only the Sun-4 or to use the Sun-4 with the hypercube. A hypercube program will use the hypercube's data processors and optionally the Weitek floating point accelerators. The CIPE programming environment provides a simple set of subroutines to activate user interface functions, specify data distributions, activate hypercube resident applications, and to communicate parameters to and from the hypercube.

Williams, Winifred I.↗
NASA NTRS1992

Field programmable gate arrays: Evaluation report for space-flight application

Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

Sandoe, Mike↗
NASA NTRS1992

Programmability in AIPS++

AIPS++ is an Astronomical Information Processing System being designed and implemented by an international consortium of NRAO and six other radio astronomy institutions in Australia, India, the Netherlands, the United Kingdom, Canada, and the USA. AIPS++ is intended to replace the functionality of AIPS, to be more easily programmable, and will be implemented in C++ using object-oriented techniques. Programmability in AIPS++ is planned at three levels. The first level will be that of a command-line interpreter with characteristics similar to IDL and PV-Wave, but with an intensive set of operations appropriate to telescope data handling, image formation, and image processing. The third level will be in C++ with extensive use of class libraries for both basic operations and advanced applications. The third level will allow input and output of data between external FORTRAN programs and AIPS++ telescope and image databases. In addition to summarizing the above programmability characteristics, this talk will given an overview of the classes currently being designed for telescope data calibration and editing, image formation, and the 'toolkit' of mathematical 'objects' that will perform most of the processing in AIPS++.

Hjellming, R. M.↗
NASA NTRS1998

Current Radiation Issues for Programmable Elements and Devices

State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

Katz, R.↗
NASA NTRS1997

Radiation Effects on Current Field Programmable Technologies

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Katz, R.↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
NASA NTRS2002

Software Safety Assurance of Programmable Logic

Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

Berens, Kalynnda↗
NASA NTRS1988

Programmable control means for providing safe and controlled medication infusion

An implantable programmable infusion pump (IPIP) is disclosed and generally includes: a fluid reservoir filled with selected medication; a pump for causing a precise volumetric dosage of medication to be withdrawn from the reservoir and delivered to the appropriate site within the body; and, a control means for actuating the pump in a safe and programmable manner. The control means includes a microprocessor, a permanent memory containing a series of fixed software instructions, and a memory for storing prescription schedules, dosage limits and other data. The microprocessor actuates the pump in accordance with programmable prescription parameters and dosage limits stored in the memory. A communication link allows the control means to be remotely programmed. The control means incorporates a running integral dosage limit and other safety features which prevent an inadvertent or intentional medication overdose. The control means also monitors the pump and fluid handling system and provides an alert if any improper or potentially unsafe operation is detected.

Fischell, Robert E.↗
NASA NTRS2008

Distributed solid state programmable thermostat/power controller

A self-contained power controller having a power driver switch, programmable controller, communication port, and environmental parameter measuring device coupled to a controllable device. The self-contained power controller needs only a single voltage source to power discrete devices, analog devices, and the controlled device. The programmable controller has a run mode which, when selected, upon the occurrence of a trigger event changes the state of a power driver switch and wherein the power driver switch is maintained by the programmable controller at the same state until the occurrence of a second event.

Alexander, Jane C.↗
NASA NTRS2007

Programmable Thermostats for MPLM Shell Heater Control ULF1: Thermal Performances - 1

The Multi-Purpose Logistics Module (MPLM) is the primary carrier for "pressurized" logistics to and from the International Space Station (ISS). The MPLM is transported in the payload bay of the Space Shuttle and is docked to the ISS for unloading, and reloading, of contents within the ISS shirt sleeve environment. Foil heaters, controlled originally with bi-metallic thermostats, are distributed across the outside of the MPLM structure and are utilized to provide energy to the structure to avoid exposure to cold temperatures and prevent condensation. The existing bi-metallic, fixed temperature set point thermostats have been replaced with Programmable Thermostats Modules (PTMs) in the Passive Thermal Control Subsystem (PTCS) 28Vdc shell heater circuits. The goal of using the PTM thermostat is to improve operational efficiency of the MPLM on-orbit shell heaters by providing better shell temperature control via feedback control capability. Each heater circuit contains a programmable thermostat connected to an external temperature sensor, a Resistive Temperature Device (RTD), which is used to provide continuous temperature monitoring capability. Each thermostat has programmable temperature set points and control spans. The data acquisition system uses a standard RS-485 serial interface communications cable to provide digital control capability. The PTM system was designed by MSFC, relying upon ALTEC support for their integration within the MPLM system design, while KSC performed the installation and ground checkout testing of the thermostat and RS-485 communication cable on the MPLM FM1 flight module. The PTMs were used for the first time during the STS-121/ULF1.1 mission. This paper will describe the design, development and verification of the PTM system, as well as the PTM flight performance and comparisons with SINDA thermal model predictions.

Glasgow, Shaun↗
NASA NTRS2006

Programmable Pulse-Position-Modulation Encoder

A programmable pulse-position-modulation (PPM) encoder has been designed for use in testing an optical communication link. The encoder includes a programmable state machine and an electronic code book that can be updated to accommodate different PPM coding schemes. The encoder includes a field-programmable gate array (FPGA) that is programmed to step through the stored state machine and code book and that drives a custom high-speed serializer circuit board that is capable of generating subnanosecond pulses. The stored state machine and code book can be updated by means of a simple text interface through the serial port of a personal computer.

Zhu, David↗
NASA NTRS2006

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

adaptive hardwares↗
NASA NTRS2004

A Re-programmable Platform for Dynamic Burn-in Test of Xilinx Virtexll 3000 FPGA for Military and Aerospace Applications

Field Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).

Field Programmable Gate Arrays (FPGA)↗
DOE OSTI2026

Overview of the MAST Upgrade physics programme: testing novel concepts at low aspect ratio to inform future devices

The research programme performed on the Mega Amp Spherical Tokamak (MAST) Upgrade experiment has made significant advances in developing the physics understanding of low aspect ratio tokamaks in support of the operation of ITER and design of fusion powerplants. High performance plasma scenarios have been developed to facilitate a broad programme of experiments, in which confinement is constrained by the presence of m/n = 2/1 modes that cause substantial losses of fast ions. The onset of these modes coincides with the q = 2 surface residing in a local minimum in the toroidal current density profile. The maximum electron temperature at the pedestal top, T e,ped is limited with gas fuelling to ∼350 eV to maintain regular ELMs; higher T e,ped results in a transition to a non-stationary ELM-free regime. The operational space of spherical tokamaks has been expanded into small and ELM-free regimes. Strong shaping of the last closed flux surface can induce a transition from large to small ELMs, and ELM suppression with resonant magnetic perturbations has been observed for the first time in a low aspect ratio tokamak. Negative triangularity shaping has induced a transition from ELMy H-mode to a high-performance L-mode regime for the first time in a low aspect ratio tokamak. In studies of fast ion confinement, losses of fast particles due to Global Alfvén Eigenmodes have been identified. Interactions between fast ions generated by off-axis neutral beam injection and thermal neutrals can result in significant losses of fast ions. Experiments with on- and off-axis neutral beam injection exhibit a flux pumping mechanism, where the central safety factor is held to ∼1 in the absence of sawteeth. In studies of pedestal physics, it has been found that elevated main chamber neutral pressures result in an increase in the electron density and reduction in the temperature at the pedestal top. Advances in understanding plasma exhaust include the integration of a high-performance plasma core with detached outer divertors in the X-point target configuration. A newly commissioned lower divertor cryopump reduces the lower divertor neutral pressure by up to 50%, with minimal effect on the main chamber or upper divertor. New measurements and SOLPS-ITER simulations emphasise the importance of plasma–neutral interactions on divertor detachment in the conditions accessible in experiments. Real-time control of the ionisation front location in both divertor chambers independently has been demonstrated in double null experiments, enabled by the tightly baffled divertor chambers.

MAST Upgrade↗