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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

BIB mixers

We have determined that the multi-pin 'microprocessor style' packages in which current Blocked Impurity Band (BIB) devices are mounted will not meet our IF bandwidth spec of greater than 2 GHz for a practical mixer. Hence we have started to repackage the Ga:Ge BIB devices in new microwave compatible packages. The smaller size of the microwave package mount necessitates cutting the BIB array down to include only the 3 smallest detectors: 0.2, 0.4, and 0.6 mm sq. A FIR beam incident at f/1.5 can be focussed on the smallest element for wavelengths shorter than 100 microns. A more typical (easier) beam convergence of f/3 will require 0.4 mm elements at 100 microns and 0.6 mm elements at 170 microns wavelength. Since the device capacitance (parasitic loss) scales with detector size, there is a tradeoff of speed of response and optical convenience. Our existing optics produce only the slower convergence beam, so we need to redesign the optical layout and are looking at long focal length all-reflective microscope objectives. BIB detectors and the edge-coupled microbolometers have restricted IF bandwidths, an order of magnitude less than what is possible with the Schottky-diode mixers we currently use for astronomical observations. Consequently the frequencies of the FIR laser lines must be close to the astronomical line of interest to be an effective Local Oscillator (LO). We have therefore begun a coordinated effort to discover and measure new FIR laser transition lines in close frequency coincidence with important astrophysical lines. Most of this effort involves pumping isotopic variants of known good laser molecules with laser lines from isotopic variants of CO2. We have been most successful in detecting new FIR lines in deuterated ammonia. One line in particular is very close to the frequency of HD rotational line at 2675 GHz.

Source record↗
NASA NTRS2005

Optimum Integrated Heterodyne Photoreceiver for Coherent Lidar Applications

Many coherent lidar applications, particularly airborne and space-based applications, impose stringent power and size constraints while requiring high levels of sensitivity. For this reason, optimization of the lidar heterodyne photoreceiver is one of the critical steps in ensuring full utilization of limited resources to achieve the required sensitivity. The analysis of 2-micron heterodyne receivers shows that substantial improvement of the order of 3 dB can be obtained by proper optimization of the receiver key control parameters and elimination of its parasitic capacitances by integrating the detector, its bias circuit, and the preamplifier on a single substrate. This paper describes analytical steps for defining optimum heterodyne receiver design parameters and development of experimental devices operating at 2-micron wavelength.

Amzajerdian, Farzin↗
NASA NTRS2002

Silicon base plate with low parasitic electrical interference for sensors

A microgyroscope has a baseplate made of the same material as the rest of the microgyroscope. The baseplate is a silicon baseplate having a heavily p-doped epilayer covered by a thick dielectric film and metal electrodes. The metal electrodes are isolated from the ground plane by the dielectric. This provides very low parasitic capacitive coupling between the electrodes. The thick dielectric reduces the capacitance between the electrodes and the ground plane.

Tang, Tony K.↗
NASA NTRS2009

Differential InP HEMT MMIC Amplifiers Embedded in Waveguides

Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The differential configuration makes it possible to obtain gains greater than those of amplifiers having the single-ended configuration. To reduce losses associated with packaging, the MMIC chips are designed integrally with, and embedded in, waveguide packages, with the additional benefit that the packages are compact enough to fit into phased transmitting and/or receiving antenna arrays. Differential configurations (which are inherently balanced) have been used to extend the upper limits of operating frequencies of complementary metal oxide/semiconductor (CMOS) amplifiers to the microwave range but, until now, have not been applied in millimeter- wave amplifier circuits. Baluns have traditionally been used to transform from single-ended to balanced configurations, but baluns tend to be lossy. Instead of baluns, finlines are used to effect this transformation in the present line of development. Finlines have been used extensively to drive millimeter- wave mixers in balanced configurations. In the present extension of the finline balancing concept, finline transitions are integrated onto the affected MMICs (see figure). The differential configuration creates a virtual ground within each pair of InP HEMT gate fingers, eliminating the need for inductive vias to ground. Elimination of these vias greatly reduces parasitic components of current and the associated losses within an amplifier, thereby enabling more nearly complete utilization of the full performance of each transistor. The differential configuration offers the additional benefit of multiplying (relative to the single-ended configuration) the input and output impedances of each transistor by a factor of four, so that it is possible to use large transistors that would otherwise have prohibitively low impedances. Yet another advantage afforded by the virtual ground of the differential configuration is elimination of the need for a ground plane and, hence, elimination of the need for back-side metallization of the MMIC chip. In turn, elimination of the back-side metallization simplifies fabrication, reduces parasitic capacitances, and enables mounting of the MMIC in the electric-field plane ("E-plane") of a waveguide. E-plane mounting is consistent with (and essential for the utility of) the finline configuration, in which transmission lines lie on a dielectric sheet in the middle of a broad side of the waveguide. E-plane mounting offers a combination of low loss and ease of assembly because no millimeter-wave wire bonds or transition substrates are required. Moreover, because there is no ground plane behind the MMIC, the impedance for the detrimental even (single-ended) mode is high, suppressing coupling to that mode. Still another advantage of E-plane mounting is that the fundamental waveguide mode is inherently differential, eliminating the need for a balun to excite the differential mode.

Kangaslahti, Pekka↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗
NASA NTRS2010

Optimal and Local Connectivity Between Neuron and Synapse Array in the Quantum Dot/Silicon Brain

This innovation is used to connect between synapse and neuron arrays using nanowire in quantum dot and metal in CMOS (complementary metal oxide semiconductor) technology to enable the density of a brain-like connection in hardware. The hardware implementation combines three technologies: 1. Quantum dot and nanowire-based compact synaptic cell (50x50 sq nm) with inherently low parasitic capacitance (hence, low dynamic power approx.l0(exp -11) watts/synapse), 2. Neuron and learning circuits implemented in 50-nm CMOS technology, to be integrated with quantum dot and nanowire synapse, and 3. 3D stacking approach to achieve the overall numbers of high density O(10(exp 12)) synapses and O(10(exp 8)) neurons in the overall system. In a 1-sq cm of quantum dot layer sitting on a 50-nm CMOS layer, innovators were able to pack a 10(exp 6)-neuron and 10(exp 10)-synapse array; however, the constraint for the connection scheme is that each neuron will receive a non-identical 10(exp 4)-synapse set, including itself, via its efficacy of the connection. This is not a fully connected system where the 100x100 synapse array only has a 100-input data bus and 100-output data bus. Due to the data bus sharing, it poses a great challenge to have a complete connected system, and its constraint within the quantum dot and silicon wafer layer. For an effective connection scheme, there are three conditions to be met: 1. Local connection. 2. The nanowire should be connected locally, not globally from which it helps to maximize the data flow by sharing the same wire space location. 3. Each synapse can have an alternate summation line if needed (this option is doable based on the simple mask creation). The 10(exp 3)x10(exp 3)-neuron array was partitioned into a 10-block, 10(exp 2)x10(exp 3)-neuron array. This building block can be completely mapped within itself (10,000 synapses to a neuron).

Duong, Tuan A.↗
NASA NTRS2010

Temperature Dependence of Thin Film Spiral Inductors on Alumina Over a Temperature Range of 25 to 475 C

In this paper, we present an analysis of inductors on an Alumina substrate over the temperature range of 25 to 475 C. Five sets of inductors, each set consisting of a 1.5, 2.5, 3.5, and a 4.5 turn inductor with different line width and spacing, were measured on a high temperature probe station from 10 MHz to 30 GHz. From these measured characteristics, it is shown that the inductance is nearly independent of temperature for low frequencies compared to the self resonant frequency, the parasitic capacitances are independent of temperature, and the resistance varies nearly linearly with temperature. These characteristics result in the self resonant frequency decreasing by only a few percent as the temperature is increased from 25 to 475 C, but the maximum quality factor decreases by a factor of 2 to 3. These observations based on measured data are confirmed through 2D simulations using Sonnet software.

Ponchak, George E.↗
NASA NTRS2012

Feedback Augmented Sub-Ranging (FASR) Quantizer

This innovation is intended to reduce the size, power, and complexity of pipeline analog-to-digital converters (ADCs) that require high resolution and speed along with low power. Digitizers are important components in any application where analog signals (such as light, sound, temperature, etc.) need to be digitally processed. The innovation implements amplification of a sampled residual voltage in a switched capacitor amplifier stage that does not depend on charge redistribution. The result is less sensitive to capacitor mismatches that cause gain errors, which are the main limitation of such amplifiers in pipeline ADCs. The residual errors due to mismatch are reduced by at least a factor of 16, which is equivalent to at least 4 bits of improvement. The settling time is also faster because of a higher feedback factor. In traditional switched capacitor residue amplifiers, closed-loop amplification of a sampled and held residue signal is achieved by redistributing sampled charge onto a feedback capacitor around a high-gain transconductance amplifier. The residual charge that was sampled during the acquisition or sampling phase is stored on two or more capacitors, often equal in value or integral multiples of each other. During the hold or amplification phase, all of the charge is redistributed onto one capacitor in the feedback loop of the amplifier to produce an amplified voltage. The key error source is the non-ideal ratios of feedback and input capacitors caused by manufacturing tolerances, called mismatches. The mismatches cause non-ideal closed-loop gain, leading to higher differential non-linearity. Traditional solutions to the mismatch errors are to use larger capacitor values (than dictated by thermal noise requirements) and/or complex calibration schemes, both of which increase the die size and power dissipation. The key features of this innovation are (1) the elimination of the need for charge redistribution to achieve an accurate closed-loop gain of two, (2) a higher feedback factor in the amplifier stage giving a higher closed-loop bandwidth compared to the prior art, and (3) reduced requirement for calibration. The accuracy of the new amplifier is mainly limited by the sampling networks parasitic capacitances, which should be minimized in relation to the sampling capacitors.

Guilligan, Gerard↗
NASA NTRS2014

Passive Resonant Bidirectional Converter with Galvanic Barrier

A passive resonant bidirectional converter system that transports energy across a galvanic barrier includes a converter using at least first and second converter sections, each section including a pair of transfer terminals, a center tapped winding; a chopper circuit interconnected between the center tapped winding and one of the transfer terminals; an inductance feed winding interconnected between the other of the transfer terminals and the center tap and a resonant tank circuit including at least the inductance of the center tap winding and the parasitic capacitance of the chopper circuit for operating the converter section at resonance; the center tapped windings of the first and second converter sections being disposed on a first common winding core and the inductance feed windings of the first and second converter sections being disposed on a second common winding core for automatically synchronizing the resonant oscillation of the first and second converter sections and transferring energy between the converter sections until the voltage across the pairs of transfer terminals achieves the turns ratio of the center tapped windings.

Rosenblad, Nathan S.↗
NASA NTRS1976

Experimental investigation of a double-diffused MOS structure

Self-aligned polysilicon gate technology was applied to double-diffused MOS (DMOS) construction in a manner that retains processing simplicity and effectively eliminates parasitic overlap capacitance because of the self-aligning feature. Depletion mode load devices with the same dimensions as the DMOS transistors were integrated. The ratioless feature results in smaller dimension load devices, allowing for higher density integration with no increase in the processing complexity of standard MOS technology. A number of inverters connected as ring oscillators were used as a vehicle to test the performance and to verify the anticipated benefits. The propagation time-power dissipation product and process related parameters were measured and evaluated. This report includes (1) details of the process; (2) test data and design details for the DMOS transistor, the load device, the inverter, the ring oscillator, and a shift register with a novel tapered geometry for the output stages; and (3) an analytical treatment of the effect of the distributed silicon gate resistance and capacitance on the speed of DMOS transistors.

Lin, H. C.↗
NASA NTRS1988

Schottky Diode With Surface Channel

Straighforward design changes improve performance and simplify fabrication. Anode contact finger forms bridge over channel material removed to reduce parasitic shunt capacitance. Device made by standard processing techniques readily accommodating changes of design.

Bishop, William↗
NASA NTRS1989

Microwave field effect transistor

Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate, and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segments of the source and drain electrodes. The gate and drain electrodes include inactive pads remote from the active segments. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes extablish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.

Huang, Ho-Chung↗
NASA NTRS1975

Low-noise room-temperature and cryogenic mixers for 80-120 GHz

A description is given of two new mixers designed to operate in the 80-120-GHz range on 36-ft radio telescope. It is shown that for a hard-driven diode the parasitic resistance and capacitance are the primary factors influencing the design of the diode mount. A room-temperature mixer is described which achieves a single-sideband (SSB) conversion loss (L) of 5.5 dB, and a SSB noise temperature (Tm) of 500 K (excluding the IF contribution) with a 1.4-GHz IF. A cryogenically cooled version, using a quartz structure to support the diode chip and contact whisker, achieves values of L = 5.8 dB and Tm = 300 K with a 4.75-GHz IF. The mixers use high-quality Schottky-barrier diodes in a one-quarter-height waveguide mount.

Kerr, A. R.↗
NASA NTRS1992

Analysis of shielded CPW discontinuities with air-bridges

The effect of air-bridges on the performance of various coplanar waveguides (CPW) discontinuities is studied. Specifically, the coupled open-end CPW's and the short-end shunt CPW stub discontinuities are considered. The high frequency effect of the air-bridge is evaluated using a hybrid technique. At first, the frequency dependent equivalent circuit of the planar discontinuity without the air-bridge is derived using the Space Domain Integral Equation (SDIE) method. Then, the circuit is modified by incorporating the air-bridge's parasitic inductance and capacitance which are evaluated using a simple quasi-static model. The frequency response of each discontinuity with and without the air-bridge is studied and the scattering parameters are plotted in the frequency range 30-50 GHz for typical CPW dimensions.

Dib, N. I.↗
NASA NTRS1992

Negative Differential Resistance (NDR) frequency conversion with gain

The dependence of the I-V characteristic of the negative differential resistance (NDR) devices on the power level and frequency of the rf input signal has been theoretically analyzed with a modified large- and small-signal nonlinear circuit analysis program. The NDR devices we used in this work include both the tunnel diode (without the antisymmetry in the I-V characteristic) and resonant-tunneling devices (with the antisymmetry in the I-V characteristic). Absolute negative conductance can be found from a zero-biased resonant tunneling device when the applied pump power is within a small range. This study verifies the work of Sollner et al. Variable negative conductances at the fundamental and harmonic frequencies can also be obtained from both the unbiased and biased tunnel diodes. The magnitude of the negative conductances can be adjusted by varying the pump amplitude -- a very useful circuit property. However, the voltage range over which the negative conductance occurs moves towards the more positive side of the voltage axis with increasing frequency. Furthermore, the range of the pumping amplitude to obtain negative conductance varies with the parasitics (resistance and capacitance) of the device. The theoretical observation of the dependence of the I-V characteristic of the NDR devices on the power and frequency of the applied pump signal is supported by the experimental results. In addition, novel functions of a NDR device such as self-oscillating frequency multiplier and mixer with gain have been experimentally demonstrated. The unbiased oscillator have also been successfully realized with a NDR device with an antisymmetrical I-V characteristic. Finally, the applications of these device functions will be discussed.

Hwu, R. J.↗
NASA NTRS1978

Semi hemi antenna

The University of Michigan minipod, which is released from a balloon and floats down on a parachute, is designed for stratospheric testing. The present paper briefly describes the evolution of antenna designs for the minipod 1.5 GHz transceiver, which communicates with and relays information to an aircraft and ground station. The following stages are noted: ordinary monopole, crossed dipole, capacitative antenna, fat monopole, the addition of parasitic elements, and a thinner monopole with taper.

Repucci, T. A.↗
NASA NTRS2003

RF Frequency Oscillations in the Early Stages of Vacuum Arc Collapse

RF frequency oscillations may be produced in a typical capacitive charging / discharging pulsed power system. These oscillations may be benign, parasitic, destructive or crucial to energy deposition. In some applications, proper damping of oscillations may be critical to proper plasma formation. Because the energy deposited into the plasma is a function of plasma and circuit conditions, the entire plasma / circuit system needs to be considered as a unit To accomplish this, the initiation of plasma is modeled as a time-varying, non-linear element in a circuit analysis model. The predicted spectra are compared to empirical power density spectra including those obtained from vacuum arcs.

Griffin, Steven T.↗
NASA NTRS1990

High power density dc-to-dc converters for aerospace applications

Three dc-to-dc converter topologies aimed at high-power high-frequency applications are introduced. Major system parasitics, namely, the leakage inductance of the transformer and the device output capacitance are efficiently utilized. Of the three circuits, the single-phase and three-phase versions of the dual active bridge topology demonstrate minimal stresses, better utilization of the transformer, bidirectional, and buck-boost modes of operation. All circuits operate at a constant switching frequency, thus simplifying design of the reactive elements. The power transfer characteristics and soft-switching regions on the Vout-Iout plane are identified. Two coaxial transformers with different cross-sections were built for a rating of 50 kVA. Based on the single-phase dual active bridge topology, a 50 kW, 50 kHz converter operating at an input voltage of 200 Vdc and an output voltage of 1600 Vdc was fabricated. Characteristics of current-fed output make the dual active bridge topologies amenable to paralleling and hence extension to megawatt power levels. Projections to a 1 MW system operating from a 500 Vdc input, at an output voltage of 10 kVdc and a switching frequency of 50 kHz, using MOS-controlled thyristors, coaxially wound transformers operating at three times the present current density with cooling, and multilayer ceramic capacitors, suggests an overall power density of 0.075 to 0.08 kg/kW and an overall efficiency of 96 percent.

Divan, Deepakraj M.↗