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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

The Compensating Common-Gate Frontend Circuit Used as Current Source Receiver

A very low power frontend circuit using the compensating common-gate scheme is described. It combines features of the regular common-gate topology and the trans-impedance amplifier (TIA) schemes allowing designers to achieve low input impedance and sufficient bandwidth with small power consumption. It can be used as an interface between detectors and the pseudo-thyristors we developed to complete a full frontend signal chain. Simulation shows that in a 65 nm process, it is possible to achieve an input impedance <1K Ohms allowing a charge detection <6fC with 3pF parasitic capacitance, using static power below 20 micro-Watts/channel.

Fu, T.↗
DOE OSTI2020

Improved Frequency-Domain Steady-State Modeling of the Dual-Active-Bridge Converter Considering Finite ZVS Transition Time Effects

This article presents an improved analytical modeling (IAM) approach for the dual-active-bridge (DAB) converter in the frequency-domain. Specifically, finite transition times are incorporated into the improved modeling that are significant in DAB converters operated at high frequency. The IAM approach is first motivated by comparing traditional frequency-domain modeling against realistic simulation results in LTspice. Next, the IAM approach is mathematically developed in an iterative fashion, where the conventional frequency-domain approach is used as the initialization of the operational behavior of the converter. Subsequent iterations of the IAM algorithm incorporate finite rise- and falltimes of device output capacitances based on detailed switching behavior analyses, which may considerably perturb the desired modulation parameters (i.e., phase shift and zero states). While the initially proposed IAM approach demonstrates advantages over ideal modeling, it is still shown to exhibit errors when applied to device transitions with significant nonlinearity in parasitic output capacitance. To account for this, a three-slope approximation to the switching transition is then motivated and developed, which enables significantly improved steady-state prediction accuracy. Simulation and experimental results confirm unacceptable inaccuracies associated with the conventional frequency-domain modeling across a wide range of operating conditions, alongside enhanced accuracy provided by the proposed modeling approach.

14 SOLAR ENERGY↗
DOE OSTI2026

Tradeoffs in single stage drift step recovery diode generator design

A high-voltage generator of nanosecond pulses utilizing a drift step recovery diode (DSRD) as an opening switch in the compression section is designed to operate at peak voltages of 4 kV and repetition rates of 2 MHz in burst mode at reduced voltages. The generator is used to perform empirical studies on the output metrics of a DSRD generator with a focus on matching the circuit of the reverse current loop parameters and DSRD to the load. The dynamic impedance introduced by nonlinear elements in the DSRD was investigated with respect to the driving circuit by varying the number of DSRDs connected in series. Experimental results indicate that optimization of the driving circuit for the DSRD is key to minimizing losses and achieving optimal pulse compression. Furthermore, the results also indicate trends in DSRD performance as larger storage inductances and longer pumping times are used, limiting the pulse compression capabilities of a single stage DSRD generator.

Electrical properties and parameters↗
DOE OSTI2020

Characterization of an architecture for front-end pixel binning in an integrating pixel array detector

Optimization of an area detector involves compromises between various parameters like frame rate, read noise, dynamic range and pixel size. We have implemented and tested a novel front-end binning design in a photon-integrating hybrid pixel array detector using the MM-PAD- 2.0 pixel architecture. In this architecture, the pixels can be optionally binned in a 2 x 2 pixel configuration using a network of switches to selectively direct the output of 4 sensor pixels to a single amplifier input. Doing this allows a trade-off between frame rate and spatial resolution. Tests show that the binned pixels perform well, but with some degradation on performance as compared to an un-binned pixel. The increased parasitic input capacitance does reduce the signal collected per x-ray as well as increases the noise of the pixel. Here, the increase in noise is, however, less than the factor of 2 increase one would observe for binning in post-processing. Spatial scans across the binned pixels show that no measured signal intensity is lost at the inner binning unit boundaries. In the high flux regime, at a 2 x 2 pixel wide beam spot (FWHM) size, binned mode responds linearly up to a photon flux of 10 7 x-rays/s, and performs comparably with un-binned mode up to a photon flux of 10 8 x-rays/s. While this study demonstrates a proof of concept for front-end binning in integrating detectors, we also identify changes to this early-stage prototype which can further improve the performance of binning pixel structures.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Frequency Response Analysis to Monitor and Identify Changes in the Impedance of a Photovoltaic Panel Measured Online using a Power Optimizer

Photovoltaic (PV) cells are generally modeled as a current source due to photocurrent, p-n junction diodes with parasitic resistance, capacitance, and inductance. This paper proposes online frequency response analysis (FRA) to measure the impedance of a PV panel using an existing panel-level power optimizer in a PV system. The algorithm will actively perturb a small signal into a 300 W rooftop PV panel and compute its small signal impedance. The technology discussed is easy to incorporate, requires no additional hardware, doesn't alter the stability of the system, and is implemented at a steady-state point. The power optimizer initially stabilizes at an operating point and then perturbs the PV current via FRA and computes PV panel impedance. The relative standard deviation test conducted indoors under 300 W/m 2 illumination on a PV panel shows a less than 5% error rate in PV panel impedance magnitude and phase is measured using a power optimizer.

14 SOLAR ENERGY↗
DOE OSTI2022

A High-Accuracy Power Loss Model of SiC MOSFETs in Current Source Inverter Considering Current Commutation and Parasitic Parameters

Power loss estimation of power electronic devices is important to the efficiency optimization of motor drives used in many applications. However, most existing simplified power loss models of silicon carbide (SiC) MOSFETs are not sufficiently accurate due to their neglect of parasitic parameters in the current commutation loop. In addition, the loss model of the voltage source inverter (VSI) cannot be directly applied to the current source inverter (CSI) because of differences between their commutation loops. First, the commutation processes for VSIs and CSIs are compared. The voltage and current trajectories of SiC MOSFETs in the switching transition of a CSI-based motor drive system are analyzed in detail. Based on these results, the conduction and switching losses of SiC MOSFETs in CSIs are modeled considering the current commutation details. In addition, the proposed analytical model includes parasitic inductances and capacitances in the current commutation loop. Experimental results have verified that the proposed power loss model delivers higher accuracy loss predictions than the conventional loss model.

current commutation, current source inverter, powe↗
DOE OSTI2020

Quantifying Dynamic On-State Resistance of GaN HEMTs for Power Converter Design via a Survey of Low and High Voltage Devices

Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Furthermore, quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.

14 SOLAR ENERGY↗
DOE OSTI2025

Correcting impedance measurements for background parasitics to characterize circuit components in cryogenic environments

Predictable circuit response is a critical prerequisite for accurate electronic measurements. Here, we describe a powerful yet straightforward experimental method and analysis model that utilizes an affordable LCR meter in conjunction with an in situ parasitic-impedance background-correction procedure to measure the temperature-dependent impedance (magnitude and phase) of up to ten individual passive circuit elements in a single cryostat run. We show how the model unambiguously identified a ∼20× drop in capacitance for 22 μF 5XR multilayer ceramic capacitors cooled from 300 K to 360 mK in an environment with a parasitic capacitance of ∼300 pF. The same experimental procedure, based on a simple two-wire measurement, was also used to measure 10 and 22 pF thin-film capacitors and 100 MΩ thick-film resistors. The results showed that the resistor values increased by up to an order of magnitude when the devices were cooled from 300 K to 360 mK. Most importantly, we showed that the simple data-acquisition method, coupled with our analysis model, enabled the measurement of component parasitics, and effectively extended the accuracy of a commercial LCR meter beyond its manufacturer-guaranteed values for a wide range of measurement frequencies. We also showed that, in the current configuration, our simple approach is limited to a capacitance accuracy of ∼10 pF.

Carpenter, R. J. [Santa Clara Univ., Santa Clara, ↗
DOE OSTI2025

Development of a capacitance measurement for pulsed magnetic fields

Capacitance measurements are crucial for probing the electrical properties of materials. In this study, we develop and implement a capacitance measurement technique optimized for pulsed magnetic fields. Our approach employs an auto-balancing bridge method, leveraging a high-bandwidth transimpedance amplifier to mitigate parasitic contributions from coaxial cables. This technique enables precise capacitance measurements in rapidly changing magnetic fields, as demonstrated in experiments on the magnetoelectric material NiCo 2 TeO 6 . The results reveal strong magnetoelectric coupling, including a pronounced hysteresis in capacitance that coincides with magnetization measurements and an enhanced energy dissipation peak at high sweep rates. Compared to traditional LCR meter measurements in DC fields, our method exhibits excellent agreement while providing additional insight into field-induced phase transitions. This work establishes a robust methodology for capacitance measurements under extreme conditions and opens new opportunities for studying multiferroic and correlated electron systems under high magnetic fields.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Liquid-Cooled Heat Sink Optimization for Thermal Imbalance Mitigation in Wide-Bandgap Power Modules

Power semiconductor die placement on substrates used in high-power modules is generally optimized to minimize electrical parasitic (e.g., stray inductance, common-mode capacitance), taking into account the minimum spacing between semiconductor dies for thermal decoupling. The layout assumes sufficient heat spreading and transfer from dies to the cooling structure. Insulated metal substrate-based power module designs may lead to asymmetrical thermal resistance across the dies, which may cause significant temperature differences among the devices. Such unintentional thermal asymmetries can lead to oversizing the cooling system design or underusing the semiconductor power processing capability. This article proposes a thermal imbalance mitigation method that uses evolutionary optimized liquid-cooled heat sinks to improve the thermal loading among devices.

42 ENGINEERING↗
DOE OSTI2023

Enhancing the electron mobility in Si-doped (010) β-Ga 2 O 3 films with low-temperature buffer layers

We demonstrate a new substrate cleaning and buffer growth scheme in β-Ga 2 O 3 epitaxial thin films using metal–organic vapor phase epitaxy (MOVPE). For the channel structure, a low-temperature (LT, 600 °C) un-doped Ga 2 O 3 buffer was grown, followed by a transition layer to a high-temperature (HT, 810 °C) Si-doped Ga 2 O 3 channel layers without growth interruption. The (010) Ga 2 O 3 Fe-doped substrate cleaning uses solvent cleaning, followed by additional hydrofluoric acid (49% in water) treatment for 30 min before the epilayer growth. This step is shown to compensate the parasitic Si channel at the epilayer–substrate interface that originates from the substrate polishing process or contamination from the ambient. From secondary ion mass spectroscopy (SIMS) analysis, the Si peak atomic density at the substrate interface is found to be several times lower than the Fe atomic density in the substrate—indicating full compensation. The elimination of the parasitic electron channel at the epi–substrate interface was also verified by electrical (capacitance–voltage profiling) measurements. In the LT-grown (600 °C) buffer layers, it is seen that the Fe forward decay tail from the substrate is very sharp, with a decay rate of ∼9 nm/dec. X-ray off-axis rocking curve ω-scans show very narrow full width at half maximum (FWHM) values, similar to the as-received substrates. These channels show record high electron mobility in the range of 196–85 cm 2 /V⋅s in unintentionally doped and Si-doped films in the doping range of 2 × 10 16 –1 × 10 20 cm −3 . Si delta-doped channels were also grown utilizing this substrate cleaning and the hybrid LT buffers. Record high electron Hall mobility of 110 cm 2 /V⋅s was measured for sheet charge density of 9.2 × 10 12 cm −2 . This substrate cleaning, combined with the LT buffer scheme, shows the potential of designing Si-doped β-Ga 2 O 3 channels with exceptional transport properties for high-performance Ga 2 O 3 -based electron devices.

Bhattacharyya, Arkka↗
DOE OSTI2024

Power Layout Design of a GaN HEMTs-Based High-Power High-Efficiency Three-Level ANPC Inverter for 800 V DC Bus System

Multiple commutation paths exist for switching devices in a three-level active neutral point clamped (3L-ANPC) inverter operation based on the selected switching state and current direction. In addition, the capacitive coupling path of the nonswitching device is a key design aspect for enabling high voltage and high current operation of gallium nitride (GaN) switches in 3L-ANPC topology. A comprehensive study of the switching transient events of inner, outer, and clamping devices of 3L-ANPC is presented in this article. The commutation mechanisms for worst-case transient voltage overshoots (TVOs) are identified. A simplified equivalent circuit model is presented to determine the design criteria for the power layout structure's parasitic inductances. A power layout strategy satisfying the design criteria is then proposed using an insulated metal substrate power printed circuit board (PCB) to enable efficient high-power operation. The proposed design minimizes the commutation and capacitive coupling path inductances to 6 nH and 11.5 nH, respectively. This enables the fast switching operation of GaN HEMTs at 800 V dc, 36 A with a low TVO of 31% verified through experimental three-level double pulse test results. Experimental evaluation of a three-phase 3L-ANPC hardware prototype based on the proposed power layout shows 99% efficiency at 800 V, 9.5 kVA and 50 kHz switching frequency. The proposed design achieves a low case-to-ambient thermal resistance of 2.3 °C/W.

42 ENGINEERING↗
DOE OSTI2022

β -Ga 2 O 3 MESFETs with insulating Mg-doped buffer grown by plasma-assisted molecular beam epitaxy

In this work, we develop in situ Mg doping techniques in plasma-assisted molecular beam epitaxy (PAMBE) of β -Ga 2 O 3 to compensate Si dopants at the substrate epilayer growth interface and eliminate parasitic leakage paths. Both abrupt and uniform Mg doping profiles over a wide range of concentrations were achieved in β -Ga 2 O 3 epilayers grown by PAMBE. Capacitance–voltage characteristics of Si and Mg co-doped samples confirmed the compensating effect of the Mg dopants. Mg delta-doping was then integrated into a β -Ga 2 O 3 metal-semiconductor field effect transistor structure and shown to be effective in eliminating source leakage. In conclusion, the results presented here show that Mg doping is a promising way to engineer insulating buffer layers for β -Ga 2 O 3 lateral devices grown by PAMBE.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Ultra-thin on-chip ALD LiPON capacitors for high frequency application

Multi-layer ceramic capacitors have been used for high frequency decoupling application due to a lower overall impedance leading to fast current response. However, high parasitic inductance limits the application of these capacitors in ultra-high frequency domain. Thus, Multlayer Ceramic Capacitors (MLCCs) are placed close to the IC to improve circuit efficiency and reduce inductance. With next generation applications, the demand for frequency range has further increased which not only requires enhanced capacitor material but improved manufacturing techniques to limit the inductive path. Here, we demonstrate ALD of two different polymorphs of ultra-thin film lithium phosphorus oxynitride (LiPON) as an inorganic solid state electrolyte (SSE) for on chip capacitors for decoupling application. Both the LiPON capacitors shows an electric double layer behavior with a capacitance of 15 μF/cm 2 and a low leakage current (<20 nA/cm 2 ) at 2V. The LiPON shows EDLC behavior up to 10 kHz and beyond, both the polymorphs show an electrostatic behavior with a high dielectric constant (14). Furthermore, this dual frequency behavior along with low parasitic inductance and on chip integration allows for operation in extended frequency ranges.

25 ENERGY STORAGE↗
DOE OSTI2020

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. Furthermore, these results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

42 ENGINEERING↗
DOE OSTI2025

Monolithic optoelectronic circuit design for on-chip terahertz applications

We demonstrate a monolithic coplanar stripline platform for on-chip terahertz (THz) generation, transmission, and detection, addressing key challenges of mode purity, bandwidth, and referencing. Capacitive coupling of the photoconductive generator switch enforces pure odd-mode propagation, increases THz field strength, and extends the operational frequency range, achieving 0.05–1.4 THz. Our architecture enables fully monolithic fabrication with amorphous silicon switches, in situ field referencing, and galvanic isolation between generation and detection. Finite-element simulations and experiments confirm that suppressing parasitic modes improves signal integrity, providing a robust platform for high-fidelity THz spectroscopy, ultrafast electronics, and nanoscale quantum materials research.

Capacitive coupling↗
DOE OSTI2021

Emerging investigator series: local pH effects on carbon oxidation in capacitive deionization architectures

In this work, the effect of pH and potential is examined for the oxidation of carbon cloth electrodes used in capacitive deionization (CDI) processes. The degree of oxidation of the electrode surface, examined using the electrode's potential of zero charge (E pzc ) and measured using chronoamperometry and cyclic voltammetry, is found to be strongly correlated to the pH of the solution at the interface. Local pH measurements are examined at anodes and cathodes in full CDI and membrane-assisted capacitive deionization (MCDI) cells at cell voltages ranging from 0.3–1.2 V. The cathode is shown to be basic under charging potentials while the anode is found to be acidic. This local pH is found to be highly transient during charging and discharging in CDI cells while the pH is found to be relatively static in the MCDI cells, maintaining a basic pH at the cathode and an acidic pH at the anode even when the cell is discharged. Ion exchange membranes (IEM) are found to have two functions: (1) limiting co-ion expulsion that results from specific ion adsorption and (2) limiting the effects of parasitic Faradaic reactions on the separation process by stabilizing the local pH thereby mitigating dissolved oxygen reduction at the cathode and lessening carbon oxidation at the anode. Performance comparisons including the salt adsorption capacity and charge efficiency are also compared for these systems.

54 ENVIRONMENTAL SCIENCES↗
DOE OSTI2021

Addressing Spacer Channel Resistances in MCDI Using Porous and Pliable Ionic Conductors

Membrane capacitive deionization (MCDI) is a unique electrochemical separations platform that allows for energy recovery during electrode regeneration. Similar to other electrochemical separation technologies producing deionized water (e.g. electrodialysis), ohmic resistances in the spacer channel significantly hampers the performance and energy efficiency of the process. This work devised a series of ionomer coated nylon mesh nets to address spacer channel resistances in MCDI. Under constant current operation, the ionomer coated nylon meshes displayed a 300 mV lower cell voltage rise during deionization while sustaining the same deionization rate. Furthermore, energy recovery was improved by 1.4x to 5.5x depending on the saline feed concentration. The lower cell voltage rise during deionization combined with the greater energy recovery with ionomer coated meshes resulted in energy normalized adsorbed salt (ENAS) values that were 2x to 3x greater. Addressing the spacer channel resistances in MCDI allowed for 8% to 19% increase in current density without the cell voltage exceeding 1.6 V—the upper bound set for mitigating parasitic reactions. Operating at higher current density leads to smaller MCDI units for a given deionization requirement and has implications for reducing the capital costs of the MCDI unit.

Palakkal, Varada Menon (ORCID:0000000317038323)↗