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At least 37 records · Page 2

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗

Immunity Study: Port Impedance Measurement of PMU and PCI testing under EMP

With the increased requirements of real-time grid monitoring, disturbance location, and situation awareness, Phasor Measurement Units (PMUs) have become more critical for the Wide Area Measurement System (WAMS). However, the vulnerability of PMUs has not been well studied, especially under electromagnetic pulse (EMP) scenarios. The stable operation of the power system will be affected directly once EMP damages them. Therefore, studying their immunity to EMP events is urgent and necessary. In this paper, the effective impedance measurement scheme and pulsed current injection (PCI) testing are proposed for the port impedance measurement and immunity levels of PMUs. The equivalent non-uniform transmission line model is established to eliminate the impact of the fixture in the de-embedding process. Then, the circuit of the pulsed current generator is set to generate a damping sinusoid, and the double exponential wave is applied to the port. Finally, using measured impedance as a generator load, the voltage and current responses of different ports are calculated in the PCI testing simulation. In conclusion, results reveal the characteristics of port impedance, waveforms of voltage and current, and distribution of accumulative energy. The relation between port impedance and the waveforms is discussed.

42 ENGINEERING↗

Performance Evaluation and Loss Modeling of WBG Devices based on a Novel Double-Pulse Test Method for Current Source Inverter

Careful measurements of the power device characteristics are necessary to accurately estimate a power converter's losses and efficiency. The conventional double-pulse test (DPT) circuit is a well-known method to implement this laboratory characterization of power devices and power modules. However, the switching characteristics of a power device depend on the power electronics circuit in which it is connected as well as the power circuit's physical layout, in addition to the device's internal structure. Hence, the conventional DPT circuit configuration, which is tailored for a standard voltage-source inverter (VSI), is not well-suited for a current-source inverter (CSI). This paper demonstrates a previously-proposed CSI-based DPT measurement technique that is appropriate for normal CSI operation. The characteristics of SiC MOSFETs and series-connected SiC Schottky diodes used in a CSI are measured using this improved technique while taking temperature effects into account to yield more accurate loss predictions. The CSI losses, including the switching and conduction losses of SiC MOSFETs and SiC Schottky diodes, have been modeled using this approach. The total CSI losses and efficiency have been estimated based on the CSI DPT results and loss models.

42 ENGINEERING↗

Signal processing to reduce dark noise impact in precision timing

We introduce a technique to mitigate the effects of low frequency noise on precision timing. The example of Dark Count Noise Rate (DCR) in Silicon Photomultipliers (SiPMs) is emphasized. This technique exploits the correlation between time shifts on the leading edge of a signal and the residual slope of the baseline (due to noise) which remains after baseline subtraction. In fast timing applications (such as for Time-of-flight particle ID) the signal arrival time is typically captured on the signal leading edge. The signal risetime is often fixed by the physics of the sensor and input circuit. Then accurate pulse timing can be achieved by correcting a leading edge threshold time (depending on a slope proportional to both the Amplitude and the risetime) to a “constant fraction” time. This compensation for time walk due to amplitude fluctuations breaks down once we introduce interference from low frequency noise on the leading edge. In this paper we demonstrate that an additional measurement of the slope at threshold can be used to correct for this noise jitter.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

SiC and GaN Devices With Cryogenic Cooling

This article presents the cryogenically cooled application for wide bandgap (WBG) semiconductor devices. Characteristics of silicon carbide (SiC) and gallium nitride (GaN) at cryogenic temperatures are illustrated. SiC MOSFETs exhibit increased on-state resistance and slower switching speed at cryogenic temperatures. However, cryogenic cooling provides low ambient temperature environment and thus enables the SiC converter to operate at lower junction temperature to achieve higher efficiency compared to room temperature cooling. A cryogenically cooled MW-level SiC inverter prototype is developed and demonstrated the feasibility of operating high-power SiC converter with cryogenic cooling. GaN HEMTs exhibit more than five times on-state resistance reduction and faster switching speed at cryogenic temperatures which makes GaN HEMTs an excellent candidate for cryogenic power electronics applications. The significantly reduced on-state resistance of GaN devices provides the possibility to operate them at a current level much higher than rated current at cryogenic temperatures. A GaN double pulse test (DPT) circuit is constructed and demonstrated that GaN HEMTs can operate at nearly four times of rated current at cryogenic temperatures. Challenges of utilizing WBG device with cryogenic cooling are discussed and summarized.

42 ENGINEERING↗

Magnetics, Inc. 0077894A7 (Datasheet)

Description of Core Under Test (CUT). Magnetics, Inc. 0077894A7 is a powder core material having low loss and high saturation fields. Known for the marketing name Kool Mu, was transformed by taking the known magnetic material, Sendust, and altered the manufacturing process to lower core losses. Possessing these specific properties makes it ideal for power factor correction circuits as well Pulse and Flyback Transformers. In-Line Noise Filters and Inductors are also common due to the near zero magnetostriction. Exhibits a potential saturation induction of 1 T.

36 MATERIALS SCIENCE↗

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗

Evaluating pulse-shaping capabilities of next-generation pulsed power architectures

This project evaluated the pulse shaping capabilities of next-generation pulsed power (NGPP) architectures. NGPP architectures share several common attributes including multiple independent pulse-generation lines, a radial water-insulated impedance transformer, and a central vacuum insulated load region. A multi-module circuit model was developed, incorporating independent pulse-generation lines and a 2-D transmission line mesh of the radial impedance transformer to assess the effects of azimuthal asymmetry in pulse-shaped experiments. Circuit model simulations demonstrated that NGPP architectures are able to produce the the desired current pulse shapes for exemplar NGPP experiments. Additionally, the project explored automated methods for experiment design, including derivative -ree optimization and machine learning. Pulse-shaped experiments require designers to determine machine parameters that reliably produce the desired current pulse at the load, a process that typically relies on expert knowledge and iterative adjustments using the Z circuit model. Given the increased complexity of NGPP systems, this manual approach may be impractical. While the evaluated methods do not eliminate the need for manual iteration, they can reduce the time required for experiment design. Derivative-free optimization automates much of the trial-and-error process, providing a close starting point for manual adjustments or making small modifications to near-final designs. Meanwhile, deep neural network methods can generate a good qualitative match to the desired current pulse in under one second without requiring circuit model simulations.

42 ENGINEERING↗

Open Radiation Monitoring: Histogram Builder Module Design

The Open Radiation Monitoring Project seeks to develop and demonstrate a modular radiation detection architecture designed specifically for use in arms control treaty verification (ACTV) applications that will facilitate rapid development of trusted systems to meet the needs of potential future treaties. A modular architecture can be used to reduce more complex systems to a series of single purpose building blocks, thereby facilitating equipment inspection and in turn building trust in the equipment by all treaty parties. Furthermore, a modular architecture can be used to control data flow within the measurement system, reducing the risk of "hidden switches" and constraining the amount of sensitive information that could potentially be inadvertently leaked. This report details the first revision of a prototype circuit that will convert analog pulses directly into a histogrammed data set for further processing. The circuit was designed with both spectroscopy and multiplicity analysis in mind but can, in principle, be used to reduce any raw data stream into a histogram. The number of output channels is limited, and the histogram bin ranges are user configurable to allow for non-uniform and discontinuous bins, which makes it possible to restrict the information being passed down stream if desired. Pulse processing relies entirely on analog circuitry and non- programmable logic, which enables operation without the need for a central processor or other programmable control unit. The circuit remains untested under the Open Radiation Monitoring project due to the closure of the sponsoring program. However, further development and testing is scheduled to take place in support of a purpose-built trusted verification system development effort known as COGNIZANT, which demonstrates the potential benefit of developing a suite of modular trusted system components.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Power supply circuit with multiple stages for converting high voltage to low voltage and power train having the same

A power supply circuit for converting a first voltage to a second voltage where the first voltage is greater than the second voltage, and a power train having the same, are provided. The power supply circuit may have multiple stages and each stage of the power supply circuit may include a first circuit block configured to provide a start-up power to a second circuit block; a second circuit block configured to generate a Pulse-Width-Modulation (PWM) signal that controls a pulse duration of a transistor; a third circuit block configured to activate or deactivate the transistor based on the PWM signal; a fourth circuit block configured to reset a magnetic flux in a transformer to a zero state when the transistor is deactivated; and a fifth circuit block configured to maintain an output of a stage below a predetermined value by adjusting a voltage across the transformer.

Singh, Brij N.↗

Extending XACC for Quantum Optimal Control

Quantum computing vendors are beginning to open up application programming interfaces for direct pulse-level quantum control. With this, programmers can begin to describe quantum kernels of execution via sequences of arbitrary pulse shapes. This opens new avenues of research and development with regards to smart quantum compilation routines that enable direct translation of higher-level digital assembly representations to these native pulse instructions. In this work, we present an extension to the XACC system-level quantum-classical software framework that directly enables this compilation lowering phase via user-specified quantum optimal control techniques. This extension enables the translation of digital quantum circuit representations to equivalent pulse sequences that are optimal with respect to the backend system dynamics. Our work is modular and extensible, enabling third party optimal control techniques and strategies in both C++ and Python. We demonstrate this extension with familiar gradient-based methods like gradient ascent pulse engineering (GRAPE), gradient optimization of analytic controls (GOAT), and Krotov's method. Our work serves as a foundational component of future quantum-classical compiler designs that lower high-level programmatic representations to low-level machine instructions.

Nguyen, Thien↗

Direct current momentary circuit interrupter

A momentary circuit interrupter in series connection with a mechanical switch to provide protection against short circuit faults in a DC power circuit. The momentary circuit interrupter injects a transient voltage pulse via a pulse transformer to reduce a DC fault current to near zero in a DC circuit branch, thus allowing the mechanical switch to disconnect the faulty branch under a near zero-current condition. The power electronic circuit on the primary side of the transformer controls the discharge of a plurality of pre-charged capacitors to generate the transient voltage pulse during the fault interruption process, but otherwise does not incur any power loss during normal operation. The secondary winding of the pulse transformer conducts the main DC current, and is highly conductive to minimize the conduction power loss. The invention provides ultrafast response to a short circuit fault (even faster than solid-state circuit breakers and much faster than hybrid circuit breakers), significantly reduced overcurrent stress in the power system, and/or ultralow conduction power losses.

Shen, Zheng John↗

High power pulse systems for surface processing

A high-power pulsed surface processing system includes insulated-gate bipolar transistors (IGBT) to replicate desirable pulse structures with high precision, at low cost, and with high reliability within a single system. The pulsed surface processing system includes a power supply, an anode and a cathode, a dual gate driver supplying power to one or more IGBT gates, and one or more capacitor banks. Pulse formation software controls the timing and duration of electrical pulses to the electrodes. A freewheeling diode protects the system from an abrupt reduction of current in the circuit. The high-power pulsed surface processing system may be used to control versatile and complex pulse structures while with precise control of instantaneous pulse powers, pulse timing, and process control. The inclusion of dual gate drivers also offers the ability for multiple pulsers to be created and “slaved” together for a wide variety of custom processes.

Tian, Hui↗

Delay-resolved spectroscopy in terahertz photonic circuits

Photonic integrated circuits incorporating intersubband transitions are ideal for mid-infrared and terahertz nanophotonics. However, the design of epitaxies has long been inhibited by two factors: the modest predictivity of ab initio theory and the absence of absolute intersubband gain and loss measurements under operating conditions. Existing measurements either yield inaccurate gain profiles or do not accurately assess dependence on frequency, bias, and temperature. Here, we present a delay-resolved absolute-referencing method for accurate gain evaluation without these limitations, addressing a long-standing challenge. By creating a photonic circuit that allows broadband pulses to traverse different lengths of a gain medium, we measure the absolute transmission of intersubband structures. Gain profiles match theoretical predictions at lower temperatures, with gain and dispersion clamping after lasing, and faster-than-expected degradation occurs at higher temperatures. Our approach provides a precise experimental evaluation of temperature-dependent gain performance and gives insight into optimizing temperature performance and frequency comb designs.

Optical spectroscopy↗

A custom high-stability pulse generator for the test of a novel in-situ magnetic sensor developed to detect radiation damage in undulators

High-performance analog-to-digital converters (ADC) have been widely applied in many areas of science. For instance, magnetic field measurements based on the Faraday’s induction law require high-precision voltmeters to measure induced voltages. In this study in the context of free-electron lasers technology, the Magnetic Measurements Team at SLAC National Accelerator Laboratory proposed a novel in-situ radiation damage detection system (RDDS) for detecting small field variations in undulators. The system measures the flux change in a flexible printed-circuit coil attached to the magnet array during the undulator gap movement. The gap movement changes the magnetic field, which induces a voltage signal in the coil that is measured and integrated with an ADC. Although the system is capable of detecting relative flux changes better than 100 ppm, drift in the ADC’s gain or offset can cause apparent changes in the relative flux. This paper describes the first attempt to developed a high-precision verification circuit to perform ADC testing in the framework of the novel RDDS. The circuit generates a reference voltage pulse with a voltage–time integral relative precision better than 50 ppm for a few hundreds of mVs — the typical order of magnitude measured with the RDDS. The circuit’s design combines a fast and precise switch with a low-noise voltage reference. Long-term measurements allowed statistical analysis and showed that averaging the voltage–time integral of ten pulses gives the required 50 ppm stability. Moreover, reproducibility tests confirmed that the circuit’s output is invariable under small power supply instabilities and equipment shutdown. Instruments and applications designed to quantify the magnetic field by integrating voltage signals may use the pulse generator proposed in this paper for verification purposes.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗