Solid state shift register as a data storage device
MOSFET shift register for data storage
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MOSFET shift register for data storage
An electronic shift-register memory at the molecular level is described. The memory elements are based on a chain of electron-transfer molecules and the information is shifted by photoinduced electron-transfer reactions. This device integrates designed electronic molecules onto a very large scale integrated (silicon microelectronic) substrate, providing an example of a 'molecular electronic device' that could actually be made. The design requirements for such a device and possible synthetic strategies are discussed. Devices along these lines should have lower energy usage and enhanced storage density.
Magnetic-shift-register circuit controls bidirectional operations of a phase-pulsed step motor. The circuit draws no power in standby, is nonregenerative, and is insensitive to switching transients.
Preliminary study of alternate shift registers for eight-pole commutator
Pseudonoise sequence generation with three-tap linear feedback shift registers
Pseudonoise sequence generation with 3-tap linear feedback binary shift registers, citing reduction theorems
Synthesis of pseudorandom distribution for sum values in feedback shift registers
A study of the linear feedback shift registers corresponding to a subset of nonprimitive irreducible polynomials over GF(2) has uncovered a class of sequences with interesting structures and cyclic correlation properties. These families of sequences are made up of interleaved identical sequences which are from primitive irreducible polynomials. Furthermore, they have correlation functions which are two or three valued, being constant at zero or a small value throughout most of their length with the exception of a small number of impulses. Each interval between such impulses on the correlograms uniquely corresponds to (and thus uniquely identifies) the member sequence or sequences producing it. It is shown that these families of sequences have direct application as error-correcting codes.
Binary devices are used to construct an m-ary linear feedback shift register.
Linear feedback function for r-stage feedback shift register resulting in equal length branchless cycles
There is described a simple first-in, first out (FIFO) magnetic bubble domain shift register which has continuous data storage capability. In a preferred embodiment, two parallel detector branches are associated with a main storage loop. The bubbles in the storage loop are replicated toward each detector branch by passive replicators in the storage loop. Annihilators associated with each of the replicators and each of the detectors are arranged an appropriate distance from the replicators so that selective energization of the annihilators permits certain bits to propagate to one detector and other bits to propagate to the other detector. Connection of the detectors in an appropriate bridge circuit permits full data rate reclamation.
Two alternative input sequences are commonly employed in correlation chromatography (CC). They are sequences derived according to the algorithm of the feedback shift register (i.e., pseudo random binary sequences (PRBS)) and sequences derived by using the uniform random binary sequences (URBS). These two sequences are compared. By applying the "cleaning" data processing technique to the correlograms that result from these sequences, we show that when the PRBS is used the S/N of the correlogram is much higher than the one resulting from using URBS.
A number of efficient new algorithms for generating digital pseudonoise are presented. The algorithms are efficient because a large number of new pseudorandom bits are generated at each iteration of a computer implementation or at each clock pulse of a hardware implementation. The maximal-length shift register sequences obtained have good randomness properties. Some of the properties of p-n sequences are reviewed and the results of an extensive statistical evaluation of the pseudonoise are presented.
Computer circuit performing both counting and shifting logic operations also capable of miniaturization and integration in basic circuits
Register requiring two integrated circuits per stage has nominal power dissipation of 3.5 mW per stage, its use eliminates reset pulse, allowing data transfer to occur in less than 1 microsecond, and eliminates power application to both right and left portions of the register simultaneously.
Document summarizes state-of-the-art in data processing techniques on-board spacecraft, and serves as an aid for personnel requiring tutorial knowledge of ultrareliable data processing techniques.
Parallelled charge transfer channels have multiple-phase-clocked gate electrodes overspanning them in one of a number of arrangements conditioning the transfer of charge packets in opposing directions in adjacent charge transfer channels. Three-phase, four-phase, five-phase and six-phase clocking arrangements constructed in three layers of polysilicon embody the invention.
Overall design of filter combines radix converter with ADC in single functional unit that directly converts analog input to its negative binary representation. Four basic elements of filter are fixed register, shift register, counter, and accumulator.