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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective

The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.

gate-all-around transistors↗
DOE OSTI2022

The effect of residual palladium on the performance of organic electrochemical transistors

Organic electrochemical transistors are a promising technology for bioelectronic devices, with applications in neuromorphic computing and healthcare. The active component enabling an organic electrochemical transistor is the organic mixed ionic-electronic conductor whose optimization is critical for realizing high-performing devices. In this study, the influence of purity and molecular weight is examined for a p-type polythiophene and an n-type naphthalene diimide-based polymer in improving the performance and safety of organic electrochemical transistors. Our preparative GPC purification reduced the Pd content in the polymers and improved their organic electrochemical transistor mobility by ~60% and 80% for the p- and n-type materials, respectively. These findings demonstrate the paramount importance of removing residual Pd, which was concluded to be more critical than optimization of a polymer’s molecular weight, to improve organic electrochemical transistor performance and that there is readily available improvement in performance and stability of many of the reported organic mixed ionic-electronic conductors.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2021

Strain-insensitive intrinsically stretchable transistors and circuits

An all-elastomer strain engineering approach, which uses patterned elastomer layers with tunable stiffnesses, can be used to create intrinsically stretchable transistor arrays with a device density of 340 transistors cm -2 and strain insensitivity of less than 5% performance variation when stretched to 100% strain. Intrinsically stretchable electronics can form intimate interfaces with the human body, creating devices that could be used to monitor physiological signals without constraining movement. However, mechanical strain invariably leads to the degradation of the electronic properties of the devices. Here we show that strain-insensitive intrinsically stretchable transistor arrays can be created using an all-elastomer strain engineering approach, in which the patterned elastomer layers with tunable stiffnesses are incorporated into the transistor structure. By varying the cross-linking density of the elastomers, areas of increased local stiffness are introduced, reducing strain on the active regions of the devices. This approach can be readily incorporated into existing fabrication processes, and we use it to create arrays with a device density of 340 transistors cm -2 and a strain insensitivity of less than 5% performance variation when stretched to 100% strain. We also show that it can be used to fabricate strain-insensitive circuit elements, including NOR gates, ring oscillators and high-gain amplifiers for the stable monitoring of electrophysiological signals.

42 ENGINEERING↗
DOE OSTI2024

Device and material investigations of GaN enhancement-mode transistors for Venus and harsh environments

This Letter reports the device and material investigations of enhancement-mode p-GaN-gate AlGaN/GaN high electron mobility transistors (HEMTs) for Venus exploration and other harsh environment applications. The GaN transistor in this work was subjected to prolonged exposure (11 days) in a simulated Venus environment (460 °C, 94 bar, complete chemical environment including CO2/N2/SO2). The mechanisms affecting the transistor performance and structural integrity in harsh environment were analyzed using a variety of experimental, simulation, and modeling techniques, including in situ electrical measurement (e.g., burn-in) and advanced microscopy (e.g., structural deformation). Through transistor, Transmission Line Method (TLM), and Hall-effect measurements vs temperature, it is revealed that the mobility decrease is the primary cause of reduction of on-state performance of this GaN transistor at high temperature. Material analysis of the device under test (DUT) confirmed the absence of foreign elements from the Venus atmosphere. No inter-diffusion of the elements (including the gate metal) was observed. The insights of this work are broadly applicable to the future design, fabrication, and deployment of robust III-N devices for harsh environment operation.

Physics↗
NASA NTRS2004

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Phillips, Thomas A.↗
NASA NTRS2006

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Phillips, Thomas A.↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
DOE OSTI2022

Effective Selective Area Doping for GaN Vertical Power Transistors Enabled by Innovative Materials Engineering

GaN vertical power transistors have emerged as promising candidates for future high efficiency high power electronic applications, with the potential to outperform conventional GaN lateral power devices in terms of power, breakdown, and avalanche characteristics. However, the development of current GaN vertical power transistors is seriously hindered by the poor materials performance of selective area doped p-n junctions. A mechanistic understanding of these fundamental materials issues is essential in order to achieve high performance selective area doped p-n junctions and consequently to advance the GaN vertical power transistor technology. To address this challenge, we carried out a comprehensive research program that advance fundamental knowledge in the selective area doping for GaN materials, and which will lead to the development of high performance GaN vertical power transistors. First, we developed innovative fabrication processes, including novel surface etching, surface passivation, and metalorganic chemical vapor deposition (MOCVD) growth, which provided enhanced opportunities for solving the unique challenges of selective area doping in GaN materials. Second, we performed a fundamental materials study using powerful characterization methods including transmission electron microscopy (TEM), ultraviolet (UV-), x-ray and angle-resolved photoelectron spectroscopy (UPS/XPS/ARPES), electron holography, and cathodoluminescence (CL); Third, we investigated several related issues, including Mg incorporation, polarization effects in carrier transport, and non-ideal material effects, which have rarely been explored so far. At the end of this project, we successfully demonstrated (1) fundamental understanding of selective area etching, regrowth, and doping of GaN, and associated knowledge on defects, interface, and breakdown properties. (2) Effective etch and regrowth processing recipes to achieve etch/regrowth GaN p-n diodes with very low leakage of 3.5 nA at 600 V, which meets the ARPA-E target. (2) High performance vertical GaN p-n didoes and vertical junction termination extension (JTE) devices with breakdown voltage of ~ 2 kV, and breakdown electric field of ~ 3.5 MV/cm, which are close to the performance limit of GaN. The successful outcome has resulted in new fundamental understandings in the selective area doping and regrowth process for GaN, which will lead to groundbreaking GaN vertical transistors for high performance next generation power electronics.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS2004

T-shaped emitter metal heterojunction bipolar transistors for submillimeter wave applications

We report on the development of submillimeter wave transistors at JPL. The goal of the effort is to produce advance-reliable high frequency and high power amplifiers, voltage controlled oscillators, active multipliers, and high-speed mixed-signal circuits for space borne applications. The technology in development to achieve this is based on the Indium Phosphide (InP) Heterojunction Bipolar Transistor (HBT). The HBT is well suited for high speed, high power and uniform (across wafer) performance, due to the ability to tailor the material structure that electrons traverse through by well-controlled epitaxial growth methods. InP with its compatible lattice matched alloys such as indium gallium arsenide (InGaAs) and indium aluminium arsenide (InAlAs) provides for high electron velocities and high voltage breakdown capabilities. The epitaxial methods for this material system are fairly mature, however the implementation of high performance and reliable transistors are still under development by many laboratories. Our most recently fabricated, second generation mesa HBTs at JPL have extrapolated current gain cutoff frequency (FJ of 142GHz and power gain cutoff frequency (Fm,) of approximately 160GHz. This represents a 13% and 33% improvement of Ft and F, respectively, compared to the first generation mesa HBTs [l]. Analysis based on the University of California, Santa Barbara (UCSB) device model, RF device characteristics can be significantly improved by reducing base contact resistance and base metal contact width. We will describe our effort towards increasing transistor performance and yield.

transistor↗
DOE OSTI2020

Organic Microbial Electrochemical Transistor Monitoring Extracellular Electron Transfer

Abstract Extracellular electron transfer (EET) denotes the process of microbial respiration with electron transfer to extracellular acceptors and has been exploited in a range of microbial electrochemical systems (MESs). To further understand EET and to optimize the performance of MESs, a better understanding of the dynamics at the microscale is needed. However, the real‐time monitoring of EET at high spatiotemporal resolution would require sophisticated signal amplification. To amplify local EET signals, a miniaturized bioelectronic device, the so‐called organic microbial electrochemical transistor (OMECT), is developed, which includes Shewanella oneidensis MR‐1 integrated onto organic electrochemical transistors comprising poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) combined with poly(vinyl alcohol) (PVA). Bacteria are attached to the gate of the transistor by a chronoamperometric method and the successful attachment is confirmed by fluorescence microscopy. Monitoring EET with the OMECT configuration is achieved due to the inherent amplification of the transistor, revealing fast time‐responses to lactate. The limits of detection when using microfabricated gates as charge collectors are also investigated. The work is a first step toward understanding and monitoring EET in highly confined spaces via microfabricated organic electronic devices, and it can be of importance to study exoelectrogens in microenvironments, such as those of the human microbiome.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2023

Scaling and statistics of bottom-up synthesized armchair graphene nanoribbon transistors

Bottom-up assembled nanomaterials and nanostructures allow for the studies of rich and unprecedented quantum-related and mesoscopic transport phenomena. However, it can be difficult to quantify the correlations between the geometrical or structural parameters obtained from advanced microscopy and measured electrical characteristics when they are made into macroscopic devices. Here, we propose a strategy to connect the nanomaterial morphologies and the device performance through a Monte Carlo device model and apply it to understand the scaling trends of bottom-up synthesized armchair graphene nanoribbon (GNR) transistors. A new nanofabrication process is developed for GNR transistors with channel length down to 7 nm. Further, the impacts of the GNR spatial distributions and the device geometries on the device performance are investigated systematically through comparison of experimental data with the model. Through this study, challenges and opportunities of transistor technologies based on bottom-up synthesized GNRs are pinpointed, paving the way to the further improvement of the GNR device performance for future transistor technology nodes.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Water stable molecular n-doping produces organic electrochemical transistors with high transconductance and record stability

From established to emergent technologies, doping plays a crucial role in all semiconducting devices. Doping could, theoretically, be an excellent technique for improving repressively low transconductances in n-type organic electrochemical transistors – critical for advancing logic circuits for bioelectronic and neuromorphic technologies. However, the technical challenge is extreme: n-doped polymers are unstable in electrochemical transistor operating environments, air and water (electrolyte). Here, the first demonstration of doping in electron transporting organic electrochemical transistors is reported. The ammonium salt tetra-n-butylammonium fluoride is simply admixed with the conjugated polymer poly(N,N’-bis(7-glycol)-naphthalene-1,4,5,8-bis(dicarboximide)-co-2,2’-bithiophene-co-N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide), and found to act as a simultaneous molecular dopant and morphology-additive. The combined effects enhance the n-type transconductance with improved channel capacitance and mobility. Furthermore, operational and shelf-life stability measurements showcase the first example of water-stable n-doping in a polymer. Overall, the results set a precedent for doping/additives to impact organic electrochemical transistors as powerfully as they have in other semiconducting devices.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

A nanoscale photonic thermal transistor for sub-second heat flow switching

Abstract Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VO x )-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.

42 ENGINEERING↗
DOE OSTI2025

Mobility and threshold voltage extraction in transistors with gate-voltage-dependent contact resistance

The mobility of emerging (e.g., two-dimensional, oxide, organic) semiconductors is commonly estimated from transistor current-voltage measurements. However, such devices often experience contact gating, i.e., electric fields from the gate modulate the contact resistance during measurements, which can lead conventional extraction techniques to estimate mobility incorrectly even by a factor >2. Although this error can be minimized by measuring transistors at high gate-source bias |V gs |, this regime is often inaccessible in emerging devices that suffer from high contact resistance or early gate dielectric breakdown. Here, we propose a method of extracting mobility in transistors with gate-dependent contact resistance that does not require operation at high |V gs |, enabling accurate mobility extraction even in emerging transistors with strong contact gating. Our approach relies on updating the transfer length method (TLM) and can achieve <10% error even in regimes where conventional techniques overestimate mobility by >2×

36 MATERIALS SCIENCE↗
DOE OSTI2022

Low-temperature processed beta-phase In 2 Se 3 ferroelectric semiconductor thin film transistors

As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In 2 Se 3 , at temperature as low as 400 °C. Top gate n-channel In 2 Se 3 thin film transistors were fabricated with field-effect mobility ∼1 cm 2 V −1 s −1 , and simple polarization switching based memory results are presented.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Investigating the Effects of Individual Neutron-Induced Defects in Bipolar Junction Transistors

Here, this study investigates neutron-induced displacement damage in Bipolar Junction Transistors (BJTs) using TCAD models informed by Deep-Level-Transient-Spectroscopy (DLTS) data. These models are calibrated and validated against experimental measurements performed at various neutron fluences. Both npn and pnp transistor configurations are studied to analyze the effects of individual traps on carrier recombination and base leakage currents. In npn transistors, deep traps (0.42 eV from the conduction band) dominate at low voltages, while shallow traps (0.17 eV from the conduction band) become prominent at higher voltages. Conversely, pnp transistors have base leakage current predominantly due to deep-level traps. The study observes a notable trend in trap density versus fluence, characterized by a linear relationship on a log-log scale. These insights into defect evolution under radiation conditions are crucial for optimizing semiconductor device reliability and performance in radiation-prone environments.

42 ENGINEERING↗
DOE OSTI2025

2 kV Al 0.64 Ga 0.36 N-channel high electron mobility transistors with passivation and field plates

Abstract High voltage (∼2 kV) Al 0.64 Ga 0.36 N-channel high electron mobility transistors were fabricated with an on-resistance of ∼75 Ω. mm (∼21 mΩ. cm 2 ). Two field plates of variable dimensions were utilized to optimize the breakdown voltage. The breakdown voltage reached >3 kV (tool limit) before passivation however it reduced to ∼2 kV after Si 3 N 4 surface passivation and field plate deposition. The breakdown voltage and on-resistance demonstrated a strong linear correlation in a scattered plot of ∼50 measured transistors. The fabricated transistors were electrically characterized and benchmarked against the state-of-the-art high-voltage (> 1 kV) Al-rich (>40%) AlGaN-channel transistors in breakdown voltage and on-resistance, indicating significant progress.

Alam, Md Tahmidul (ORCID:000900086556839X)↗
NASA NTRS1974

Ultra-stable oscillator with complementary transistors

A high frequency oscillator, having both good short and long term stability, is formed by including a piezoelectric crystal in the base circuit of a first bi-polar transistor circuit, the bi-polar transistor itself operated below its transitional frequency and having its emitter load chosen so that the input impedance, looking into the base thereof, exhibits a negative resistance in parallel with a capacitive reactance. Combined with this basic circuit is an auxiliary, complementary, second bi-polar transistor circuit of the same form with the piezoelectric crystal being common to both circuits. By this configuration small changes in quiescent current are substantially cancelled by opposite variations in the second bi-polar transistor circuit, thereby achieving from the oscillator a signal having its frequency of oscillation stable over long time periods as well as short time periods.

Kleinberg, L. L.↗