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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Breakdown characteristics analysis of kV-class vertical GaN PIN rectifiers by wafer-level sub-bandgap photoluminescence mapping

This work reports analysis of the reverse-bias breakdown characteristics of homojunction gallium nitride (GaN) p–i–n (PIN) rectifiers fabricated on bulk GaN substrates. Sub-bandgap photoluminescence mapping at room temperature as a contactless, non-destructive wafer inspection method was performed to analyze the impact of material properties on grown GaN PIN diodes and to study the correlation between defect types and breakdown characteristics of vertical GaN PIN rectifiers. Under the sub-bandgap excitation, yellow luminescence is dominant. The premature breakdown characteristics of the fabricated kV-class vertical GaN PIN rectifiers with nitrogen-implanted floating guard rings are found to be associated with material defects and deep level complexes. Photoluminescence mapping has demonstrated its effectiveness in quantitative analysis of dislocations and other types of defects.

42 ENGINEERING↗
DOE OSTI2024

Optical contrast analysis of α -RuCl 3 nanoflakes on oxidized silicon wafers

α-RuCl 3 , a narrow-band Mott insulator with a large work function, offers intriguing potential as a quantum material or as a charge acceptor for electrical contacts in van der Waals devices. In this work, we perform a systematic study of the optical reflection contrast of α-RuCl 3 nanoflakes on oxidized silicon wafers and estimate the accuracy of this imaging technique to assess the crystal thickness. Via spectroscopic micro-ellipsometry measurements, we characterize the wavelength-dependent complex refractive index of α-RuCl 3 nanoflakes of varying thickness in the visible and near-infrared. Building on these results, we simulate the optical contrast of α-RuCl 3 nanoflakes with thicknesses below 100 nm on SiO 2 /Si substrates under different illumination conditions. We compare the simulated optical contrast with experimental values extracted from optical microscopy images and obtain good agreement. Finally, we show that optical contrast imaging allows us to retrieve the thickness of the RuCl 3 nanoflakes exfoliated on an oxidized silicon substrate with a mean deviation of –0.2 nm for thicknesses below 100 nm with a standard deviation of only 1 nm. Our results demonstrate that optical contrast can be used as a non-invasive, fast, and reliable technique to estimate the α-RuCl 3 thickness.

2D materials↗
DOE OSTI2026

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

Wafer-scale high-k SrTiO 3 dielectrics with rational barrier-layer design for low leakage and high charge density

High-k oxides such as SrTiO 3 promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO 3 is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO 3 films on Nb:SrTiO 3 , CaSnO 3 /Nb:SrTiO 3 , and 2-in. SiO 2 /p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO 3 and SiO 2 reduce leakage, but the ultra-wide-bandgap SiO 2 layer enables much higher operating voltages, yielding charge densities exceeding 5 × 10 13 cm −2 at room temperature—more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO 2 reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering—including wafer-scale integration on Si—provides a clear pathway to achieving higher charge densities in SrTiO 3 -based dielectric devices.

36 MATERIALS SCIENCE↗
DOE OSTI2024

A Scalable & Non-Destructive Characterization Strategy to Study Semiconductor/Dielectric Interfaces and Predict Wafer-Level Device Performance

The defect density present at the dielectric-semiconductor interface in an MOS structure directly influences the channel carrier characteristics in semiconductor devices, especially in wide bandgap material systems used in power devices. While these trap defects are typically quantified through electrical characterization of MOS-capacitor test structures, this treatment offers very little insight into the physical nature of interface defects. Such shortcomings demand a physical characterization strategy to guide fabrication optimization. X-ray photoelectron spectroscopy (XPS) is suggested as a viable technique to determine chemical data for dielectric interfaces formed using atomic layer deposition (ALD) on GaN substrates. Previously, 1-D XPS characterization has confirmed the presence of a Ga x O y interlayer between ALD dielectrics and the GaN substrate. In this work, XPS data is serially collected to form 2-D images of an ALD-Al 2 O 3 /GaN interface as a proof-of-concept experiment for in-situ XPS quality monitoring during ALD processing. The information provided by this work reveals some of the challenges for incorporating XPS characterization as an in-situ strategy during fabrication of GaN-based devices. Separately, electrical mapping of a 2-D array of ALD-Al 2 O 3 /GaN MOS-capacitor devices provide a means to quantify the spatial variations in interface quality across a single wafer. Physical characterization techniques, such as time-of-flight secondary ion mass spectroscopy, provide additional chemical information about the Al 2 O 3 /Ga x O y /GaN structure that complement the electrical mapping results. This analysis shows that a higher Ga x O y content correlates with higher interface state defects for trap energies deep in the band gap.

42 ENGINEERING↗
DOE OSTI2024

Sonic Wafering of III-V substrates for High Efficiency Cells: A path to <$0.50/W

This project developed and demonstrated Sonic Lift-off, a novel technology that enables the reuse of expensive semiconductor substrates used to manufacture high-efficiency solar cells. By using sound waves to precisely separate thin layers of material, the process significantly reduces manufacturing costs while maintaining the performance of advanced III–V solar cells. These solar cells are among the most efficient in the world and are used in space, aerospace, and emerging terrestrial applications. The results of this work show that substrate reuse can be achieved without degrading device performance, offering a pathway to more affordable, high-performance solar technologies. This advancement supports U.S. clean energy goals by enabling broader deployment of renewable energy systems and strengthening domestic manufacturing capabilities in advanced photovoltaics.

14 SOLAR ENERGY↗
DOE OSTI2024

System and method for bending crystal wafers for use in high resolution analyzers

The invention provides a method for fabricating analyzers, the method comprising providing a radiation manipulating material on a first surface of a flexible support; contacting a second surface of the flexible support to a permeable mold, wherein the mold has a first flexible support contact surface and a second surface; and applying negative pressure to the second side of the flexible support to cause the flexible support to conform to the first flexible support contact surface of the mold. Also provided is a system for fabricating crystal analyzers, the system comprising crystal structures reversibly attached to a flexible support; a porous mold reversibly contacting the flexible support, wherein the mold defines a topography; and a negative pressure applied to the flexible support to cause the crystal structures to conform to the topography.

Said, Ayman H.↗
DOE OSTI2026

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences↗
DOE OSTI2025

Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography

Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination. Here, in this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.

42 ENGINEERING↗