Results for “analog-to-digital converter (ADC)” — Page 2

DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2023

Physical Layer Security at a Point-to-Point MIMO System With 1-Bit DACs and ADCs

Low-resolution converters reduce the power consumption of wireless devices and help enable large energy-efficient arrays. In this letter, we evaluate the secrecy rate for the extreme case of 1-bit single-user multiple-input multiple-output systems following two signaling approaches. In the first method, the system uses discrete signaling. In the second, the system combines Gaussian signaling with artificial noise alongside power allocation. In the first case, we give a closed-form expression of the secrecy rate and propose an algorithm that provides near-optimal results for low signal-to-noise ratios (SNRs). Further, in the second scenario, depending on the channel state information, we suggest different precoding plans and derive a secrecy rate lower bound. At low SNR, power is allocated to the main signal. Only at high SNR is optimal power allocation effective. Moreover, knowing the eavesdropper channel greatly improves the system’s secrecy.

1-bit digital-to-analog (DAC) and analog-to-digita↗

DOE OSTI2021

Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment

ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically designed for operation at cryogenic temperatures (77 K–89 K). Cold electronics is considered to be an enabling technology for liquid argon detectors in neutrino experiments. The main function of the chip is to digitize signals from the 16-channel charge-sensitive amplifier designed at BNL (LArASIC) and send digitized signals to the data aggregator and serializer chip (COLDATA). ColdADC operates with a resolution of 12 bits and a sampling rate of 2 MS/s per channel. A complete characterization of prototype chips was conducted at cryogenic temperature, involving power consumption, noise and linearity performance. In the first DUNE Far-Detector module, 384000 data channels will be read out, corresponding to 24000 ColdADC chips. Therefore, systematic testing of ColdADC chips at cryogenic temperature is vital for the quality and reliability of DUNE Single-Phase modules. We have developed a Quality Control (QC) test stand that includes ColdADC evaluation and characterization at cryogenic temperature. The QC procedure was applied to a first batch of 33 chips, corresponding to 528 data channels. The obtained results meet all the required DUNE specifications for ColdADC. Moreover, the testing outcome allowed us to identify possibilities of performance optimization that are currently being addressed in the design of the next version of the chip. The Quality Control procedure is proved to be successful and will be a reference design for future large-batch production testing of final ColdADC ASICs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2021

Improving Signal to Noise Ratios in Ion Mobility Spectrometry and Structures for Lossless Ion Manipulations (SLIM) using a High Dynamic Range Analog-to-Digital Converter

Signal digitization is a commonly overlooked part of ion mobility-mass spectrometry (IMS-MS) workflows, yet it is a significant contributor for determining signal-to-noise ratios and MS resolution. Here we report on the integration of a 2 GS/s, 14-bit ADC with a structures for lossless ion manipulations (SLIM)-IMS-MS and compare the performance to a commonly used 8-bit ADC. The 14-bit ADC provided an effective reduction in digitized noise by factor of ~6, owing largely to the use of smaller bit sizes. The low baseline allowed the threshold voltage levels to be set very close to the MCP baseline voltage, allowing for as much signal to be acquired as possible without causing overloading or excessive digitization of MCP baseline noise. Analyses of Agilent tuning mixture ions and a complex mixture of heavy labeled phosphopeptides showed that the 14-bit ADC (compared to the 8-bit ADC) provided a modest signal-to-noise increase (~1.5 to 2-fold) for high intensity ions, such as the Agilent tuning mixture ions and the 2+ and 3+ charge states of many phosphopeptide constituents. However, signal enhancements were as much as 10-fold for low intensity ions, and the 14-bit ADC enabled discernable signal intensities otherwise lost using an 8-bit digitizer. Additionally, the 14-bit ADC required ~14-fold fewer mass spectra to be averaged to produce a mass spectrum with similar S/N as the 8-bit ADC under identical conditions, potentially providing an order of magnitude higher measurement throughput. The high resolution, low baseline, and fast speed of the new 14-bit ADC enables high performance digitization of MS, IMS-MS, and SLIM-IMS-MS spectra, and allows a much fuller picture of analyte profiles in complex mixtures to be acquired.

data acquisition, digitization, ion mobility spect↗

DOE OSTI2026

Captan+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗

DOE OSTI2026

CAPTAN+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗