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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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32 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Comparison and Discussion on Shortcircuit Protections for Silicon-Carbide MOSFET Modules: Desaturation Versus Rogowski Switch-Current Sensor

Survivability of silicon-carbide (SiC) mosfet modules during short circuit (SC) is essential for modern power electronics systems due to large economic implications. SiC mosfet modules exhibit narrow SC withstand times and generally much lower SC robustness than silicon (Si) insulated-gate bipolar transistors (IGBTs). This puts a critical concern on their utilization, further stressing the importance of reliable protection. This article presents a comprehensive analysis and discussion on the SiC mosfet module SC protection and performance comparison between conventional desaturation detection, previously used for Si IGBT protection, and Rogowski switch-current sensor (RSCS) detection. In addition, this article presents the experimental design for soft turn-off as a reaction to the SC detection to avoid excessive overshoots during the abrupt turn-off of the SC current. To perform different types of SC with various fault inductances on different temperatures, and for the sake of fair comparison under the same conditions, a gate-driver unit for 1.2 kV SiC mosfet half-bridge modules is developed containing both detection methods. The results demonstrate that both methods are successful in protecting the module in all SC types, with superiority of the RSCS detection and concerns for desaturation detection in high-inductance and high dc-bus voltage SC events.

42 ENGINEERING↗
DOE OSTI2025

A Two-Stage Current Limiting Control Strategy for Direct-Droop-Controlled Grid-Forming Inverters

This paper presents a two-stage current limiting control strategy with fault ride-through capability for the direct-droop-controlled grid-forming (GFM) inverters. The proposed approach comprises Stage 1 and Stage 2 current limiting controls. During faults, Stage 1 current limiting control instantly clamps the inverter output current magnitude to its maximum transient limit by blocking the switching pulses to the insulated-gate bipolar transistors (IGBTs) with the help of a hysteresis loop control, and Stage 2 current limiting control limits the inverter output current magnitude to its steady-state limit by regulating the amplitude and frequency of the modulating waveform utilizing the active and reactive current limiting control loops. By implementing the current limiting actions in two stages, this approach can effectively limit the over-current within a few cycles after the fault occurrence and ensure synchronism to the grid after long-term fault events. The efficacy of the proposed control approach is validated through electromagnetic transient (EMT) simulation results conducted on a single GFM inverter-based test system and the IEEE 39-bus test system with multiple GFM inverters in the PSCAD platform.

Mohiuddin, Sheik Mohammad↗
DOE OSTI2021

Highly Integrated Wide Bandgap Power Module for Next Generation Plug-In Vehicles (Final Report)

Wide bandgap devices are key enablers for high power density traction inverters. A highly integrated wide bandgap (WBG) power module enables higher temperature operation, higher inverter efficiency and overall smaller die area with the same power delivery. However, it requires careful design of the power module to take advantage of all the superior material properties that silicon carbide (SiC) provides over conventional silicon (Si) Insulated Gate Bipolar Transistor (IGBT) based design. This project developed an efficient and densely packed SiC power module for an automotive traction inverter application. Extensive study was performed to select the best performing SiC die considering a wide range of temperature variation, suitability to integrate into target packaging, robust body diode performance and overall high electrical efficiency. Multiple design ideas were explored to achieve lower stray inductance for both power loop and signal loop, uniform current distribution, compact form factor, and very high thermal performance. The final power module package includes all six inverter switches in the same module (six-pack) with die sintered at both bottom and top surfaces utilizing high performance substrate to achieve high electrical and thermal performance. Two power module variants were developed using 900 V and 1200 V devices for operating at two different high voltage levels (> 600 V HV battery). Both power modules were comprehensively characterized, and high efficiency operation of the inverter was confirmed through analysis. Finally, a complete functional inverter was built with the 1200V power modules using other essential components (HV capacitors, gate driver board, controller board, current sensor, connectors etc.) and tested using GM’s standard test procedure. There are several challenges associated with adopting WBG devices for high voltage operation. In order to assess and mitigate those challenges, GM and subrecipients of this project have conducted multiple detailed studies. This includes phase current reconstruction using integrated Rogowski coil, device junction temperature estimation using on-state gate resistance, modeling and testing the effect of high voltage and fast switching on motor insulation and bearings, partial discharge inception voltage measurement under different environmental conditions. Findings of all these studies are summarized in this report.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2022

Application of Convolutional and Feedforward Neural Networks for Fault Detection in Particle Accelerator Power Systems

High voltage converter modulators (HVCM) provide power to the accelerating cavities of the spallation neutron source (SNS) facility. HVCM experience catastrophic failures, which increase the downtime of the SNS and reduce beam time. The faults may occur due to different reasons including failures of the resonant capacitor, core saturation due to the magnetic flux, insulated-gate bipolar transistor (IGBT) failures, and others. We recently have setup a HVCM test stand to develop and test machine learning models for anomaly detection and fault prognostics. In this work, we propose binary classifiers and autoencoder architectures based on convolutional (CNN) and feedforward neural networks (FNN) to facilitate distinguishing normal from faulty waveforms coming from the HVCM during operation. The results indicate that the CNN binary classifier is the best model among the four showing very stable performance in the training and testing sets with impressive metrics of precision and recall reaching up to 99\% with a very small uncertainty. The FNN classifier shows the least performance with a large uncertainty in its metrics. The performances of the two autoencoders based on CNN and FNN were in between, showing very good performance nonetheless.

Radaideh, Majdi↗
DOE OSTI2024

High power pulse systems for surface processing

A high-power pulsed surface processing system includes insulated-gate bipolar transistors (IGBT) to replicate desirable pulse structures with high precision, at low cost, and with high reliability within a single system. The pulsed surface processing system includes a power supply, an anode and a cathode, a dual gate driver supplying power to one or more IGBT gates, and one or more capacitor banks. Pulse formation software controls the timing and duration of electrical pulses to the electrodes. A freewheeling diode protects the system from an abrupt reduction of current in the circuit. The high-power pulsed surface processing system may be used to control versatile and complex pulse structures while with precise control of instantaneous pulse powers, pulse timing, and process control. The inclusion of dual gate drivers also offers the ability for multiple pulsers to be created and “slaved” together for a wide variety of custom processes.

Tian, Hui↗
DOE OSTI2020

Three-Terminal Bipolar Junction Bottom Cell as Simple as PERC: Towards Lean Tandem Cell Processing

Silicon-based tandem cells are a potential upgrade for the dominating PERC technology and can greatly increase the conversion efficiency. A novel approach, the three-terminal (3T) tandem using interdigitated back-contact (IBC) cells, was shown to combine the advantages of four- and two-terminal tandem cells at the expense of a more complex bottom cell fabrication process. In this paper, we propose a simplified and lean PERC-like 3T bipolar junction bottom cell featuring two minority-carrier selective contacts and a single majority-carrier selective contact, and thus resembling a bipolar junction transistor architecture. We present the lean PERC-like fabrication process and explain the working principle by using current-voltage measurements of illuminated 3T IBC cells.

14 SOLAR ENERGY↗
DOE OSTI2020

Evaluation of the DC bus link capacitors and power transistor modules in the qualification testing of PV inverters

To achieve useful, fair, and cost-effective design qualification and type approval testing for PV inverters, two procedures were developed and demonstrated to evaluate the bus link capacitors and power transistor—and where applicable, its module—for long-term reliability. We evaluate the inverter under simulated use conditions with heat run tests to find the highest operating temperatures reached by these components. The procedures are demonstrated in this study with a 4-kVA class string inverter. The maximum temperature of the DC bus link capacitors was determined to be 76.4°C when the ambient temperature was at the inverter's maximum rated temperature of 60°C with derating occurring. On the other hand, the power transistor module's maximum temperature using the heat sink temperature as the index, 92.6°C, occurred in an ambient of 40.8°C when derating was not occurring. The conditions found for upper temperatures exhibited by these components are, respectively, proposed for implementation in the dry heat and thermal cycling tests in the IEC 62093 “Power conversion equipment for photovoltaic systems – Design qualification testing” international standard draft so that the levels applied in the tests are in proportion to those experienced in the field. Finally as a result, fairer evaluation of inverter reliability is realized.

14 SOLAR ENERGY↗
DOE OSTI2020

Local Environment Affects the Activity of Enzymes on a 3D Molecular Scaffold

The ability to coordinate and confine enzymes presents an opportunity to affect their performance and to create chemically active materials. Recent studies show that polymers and biopolymers can be used to scaffold enzymes, and that can lead to the modulated biocatalytic efficiency. In this work, we investigated the role of microenvironments on enzyme activity using a well-defined molecular scaffold. An enzyme, glucose oxidase (GO x ), was positioned at different locations of a three-dimensional (3D) octahedral DNA scaffold (OS), allowing the enzyme’s polyanionic environments to be altered. Using electrical sensing, based on a bipolar junction transistor, we measured directly and in real-time the enzyme’s proton generation at these different microenvironments. We found a 200% enhancement of immobilized enzyme over free GOx and about a 30% increase in catalytic rates when the enzyme was moved on the same molecular scaffold to a microenvironment with a higher local concentration of polyanions, which suggests a role of local pH on the enzymatic activity.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2022

Optimizing Sensor Count and Placement to Detect Bond Wire Lift-Offs and Surface Defects in High-Power IGBT Modules Using Low-Cost Piezo-Electric Resonators

This manuscript presents the most recent results and findings to identify bond wire lift-offs and surface defects in high-power isolated gate bipolar junction transistor (IGBT) modules. The authors of this manuscript formerly proposed a low-cost, piezoelectric resonator-based measurement unit to detect bond wire related degradation in larger IGBT modules. Since high-power IGBT modules are expensive, it was apparent that evaluating our proposed method by inducing controlled damage to fresh (new) IGBTs may not be cost-effective especially when multiple sets of data need to be captured by inducing damage to different levels. In order to overcome this limitation, IGBT bond wires have been mimicked using a 3D printed enclosure, a PCB, and copper wires with dimensions very closely resembling a real IGBT. Using this method, multiple test devices can be built at the cost of a real IGBT, and the proposed technique could be fine-tuned without damaging expensive, real IGBTs. Our recent findings can be used to determine real IGBT degradation and bond wire lift-offs using only two sensors, as opposed to six transducers used in the first iteration of the setup. In addition to optimizing the sensor count, we have also identified the best possible locations of these sensors by attempting multiple placements inside the IGBT casing.

condition monitoring↗
DOE OSTI2023

Multifunctional RF limiting amplifier

Multifunctional RF limiting amplifiers having various configurations and functions are disclosed. In a first configuration, the RF limiting amplifier includes an active load output circuit that allows one to adjust the output impedance based upon the anticipated connected load impedance. In a second configuration, the RF limiting amplifier includes a pair of emitter-followers to buffer the output of a first stage, allowing the RF limiting amplifier to drive one or more second stages. A third configuration includes a pair of RF limiting amplifiers with their outputs mixed to implement a down conversion function. The third configuration may be used to drive dual SAW resonators for detecting the presence of biological or chemical agents. The RF limiting amplifier may be implemented in either bipolar junction transistors or CMOS transistors.

Wessendorf, Kurt O.↗
DOE OSTI2022

Dual-mode oscillator for stress compensated cut resonator

Both parallel-type and serial-type dual-mode oscillators employing stress compensated cut resonators having various configurations are disclosed. Both classes of dual-mode oscillators employ multiple tank circuits to pass one frequency of the resonator and block the other frequency. The tank circuits isolate the operation of the two oscillator sub-circuits that form the dual-mode oscillator from one another. The dual-mode oscillators may be implemented with either bipolar or CMOS transistors. The parallel-type dual-mode oscillators employ inverters to provide gain. The serial-type dual-mode oscillators employ a two (or three) stage design including a follower circuit first stage and an inverting amplifier/limiter circuit second stage, with an optional intervening transimpedance amplifier stage.

Wessendorf, Kurt O.↗
DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2025

Amorphous Indium Oxide Channel FEFETs With Write Voltage of 0.9 V and Endurance >10 12 for Refresh-Free Embedded Memory

This work presents, for the first time, a back-end-of-the-line (BEOL)-compatible W-doped indium oxide (IWO) ferroelectric field-effect transistor (FEFET) with a record-low operating voltage below 0.9 V and a write speed of 20 ns while achieving a transient read current window (CW) ratio ( I LVT /I HVT ) greater than 10 4 . The device also exhibits exceptional reliability characteristics such as: 1) measured bipolar write endurance up to 10 12 cycles; 2) a fast read speed of 50 ns; 3) read endurance surpassing 10 12 cycles; and 4) retention exceeding 10 4 s at 85 ∘ C. Furthermore, a physics-based numerical model has been developed to investigate the nanoscale characteristics of BEOL FEFET devices, leveraging nucleation-limited switching in HfO 2 ferroelectrics and dc characterization to extract material and channel parameters for accurate device simulation. The simulation uncovers the stochastic switching behavior of BEOL amorphous oxide semiconductor (AOS) FEFETs and demonstrates an intrinsic switching time as low as 1 ps, highlighting the potential of BEOL AOS FEFETs for ultrafast memory applications. These results establish AOS FEFETs as a compelling candidate for high-density embedded memory applications for last-level cache (LLC) (L4) in advanced CMOS technology nodes.

1-V ferroelectric field-effect transistor (FEFET)↗
DOE OSTI2020

Spatial defects nanoengineering for bipolar conductivity in MoS 2

Understanding the atomistic origin of defects in two-dimensional transition metal dichalcogenides, their impact on the electronic properties, and how to control them is critical for future electronics and optoelectronics. Here, we demonstrate the integration of thermochemical scanning probe lithography (tc-SPL) with a flow-through reactive gas cell to achieve nanoscale control of defects in monolayer MoS 2 . The tc-SPL produced defects can present either p- or n-type doping on demand, depending on the used gasses, allowing the realization of field effect transistors, and p-n junctions with precise sub-μm spatial control, and a rectification ratio of over 10 4 . Doping and defects formation are elucidated by means of X-Ray photoelectron spectroscopy, scanning transmission electron microscopy, and density functional theory. We find that p-type doping in HCl/H 2 O atmosphere is related to the rearrangement of sulfur atoms, and the formation of protruding covalent S-S bonds on the surface. Alternatively, local heating MoS 2 in N 2 produces n-character.

36 MATERIALS SCIENCE↗