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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Physical Layer Security at a Point-to-Point MIMO System With 1-Bit DACs and ADCs

Low-resolution converters reduce the power consumption of wireless devices and help enable large energy-efficient arrays. In this letter, we evaluate the secrecy rate for the extreme case of 1-bit single-user multiple-input multiple-output systems following two signaling approaches. In the first method, the system uses discrete signaling. In the second, the system combines Gaussian signaling with artificial noise alongside power allocation. In the first case, we give a closed-form expression of the secrecy rate and propose an algorithm that provides near-optimal results for low signal-to-noise ratios (SNRs). Further, in the second scenario, depending on the channel state information, we suggest different precoding plans and derive a secrecy rate lower bound. At low SNR, power is allocated to the main signal. Only at high SNR is optimal power allocation effective. Moreover, knowing the eavesdropper channel greatly improves the system’s secrecy.

1-bit digital-to-analog (DAC) and analog-to-digita↗
DOE OSTI2023

Covariant bit threads

We derive several new reformulations of the Hubeny-Rangamani-Takayanagi covariant holographic entanglement entropy formula. These include: (1) a minimax formula, which involves finding a maximal-area achronal surface on a timelike hypersurface homologous to D(A) (the boundary causal domain of the region A whose entropy we are calculating) and minimizing over the hypersurface; (2) a max V-flow formula, in which we maximize the flux through D(A) of a divergenceless bulk 1-form V subject to an upper bound on its norm that is non-local in time; and (3) a min U-flow formula, in which we minimize the flux over a bulk Cauchy slice of a divergenceless timelike 1-form U subject to a lower bound on its norm that is non-local in space. The two flow formulas define convex programs and are related to each other by Lagrange duality. For each program, the optimal configurations dynamically find the HRT surface and the entanglement wedges of A and its complement. The V-flow formula is the covariant version of the Freedman-Headrick bit thread reformulation of the Ryu-Takayanagi formula. We also introduce a measure-theoretic concept of a “thread distribution”, and explain how Riemannian flows, V-flows, and U-flows can be expressed in terms of thread distributions.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2022

Crossing Versus Locking: Bit Threads and Continuum Multiflows

Bit threads are curves in holographic spacetimes that manifest boundary entanglement, and are represented mathematically by continuum analogues of network flows or multiflows. Subject to a density bound, the maximum number of threads connecting a boundary region to its complement computes the Ryu–Takayanagi entropy. When considering several regions at the same time, for example in proving entropy inequalities, there are various inequivalent density bounds that can be imposed. Here, we investigate for which choices of bound a given set of boundary regions can be “locked”, in other words can have their entropies computed by a single thread configuration. We show that under the most stringent bound, which requires the threads to be locally parallel, non-crossing regions can in general be locked, but crossing regions cannot, where two regions are said to cross if they partially overlap and do not cover the entire boundary. We also show that, under a certain less stringent density bound, a crossing pair can be locked, and conjecture that any set of regions not containing a pairwise crossing triple can be locked, analogously to the situation for networks.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

Let Each Quantum Bit Choose Its Basis Gates

Near-term quantum computers are primarily limited by errors in quantum operations (or gates) between two quantum bits (or qubits). A physical machine typically provides a set of basis gates that include primitive 2-qubit (2Q) and 1-qubit (1Q) gates that can be implemented in a given technology. 2Q entangling gates, coupled with some 1Q gates, allow for universal quantum computation. In superconducting technologies, the current state of the art is to implement the same 2Q gate between every pair of qubits (typically an XX-or XY-type gate). This strict hardware uniformity requirement for 2Q gates in a large quantum computer has made scaling up a time and resource-intensive endeavor in the lab. We propose a radical idea – allow the 2Q basis gate(s) to differ between every pair of qubits, selecting the best entangling gates that can be calibrated between given pairs of qubits. This work aims to give quantum scientists the ability to run meaningful algorithms with qubit systems that are not perfectly uniform. Scientists will also be able to use a much broader variety of novel 2Q gates for quantum computing. We develop a theoretical framework for identifying good 2Q basis gates on “nonstandard” Cartan trajectories that deviate from “standard” trajectories like XX. We then introduce practical methods for calibration and compilation with nonstandard 2Q gates, and discuss possible ways to improve the compilation. To demonstrate our methods in a case study, we simulated both standard XY-type trajectories and faster, nonstandard trajectories using an entangling gate architecture with far-detuned transmon qubits. We identify efficient 2Q basis gates on these nonstandard trajectories and use them to compile a number of standard benchmark circuits such as QFT and QAOA. Furthermore, our results demonstrate an 8x improvement over the baseline 2Q gates with respect to speed and coherence-limited gate fidelity.

quantum computing↗
DOE OSTI2025

A Study of Performance Portability of Low-bit Fused Matrix-Vector Multiplication Kernels in SYCL

Understanding the causes of performance gaps between a portable programming model and a vendor-specific programming model is important for improving performance portability. This paper studies performance portability of low-bit fused general matrix-vector multiplication kernels in SYCL on vendors’ graphics processing units (GPUs). This work introduces the use case, explains the kernel implementations in detail, evaluates the performance of the CUDA, HIP, and SYCL kernels on datacenter, desktop, and laptop GPUs, and investigates the causes of performance gaps. The results show that loop unrolling, kernel dispatch overhead, and sum reduction contribute to the gaps.

Jin, Zheming [ORNL] (ORCID:000000027197780X)↗
DOE OSTI2023

PyTorch Circuit-Aware Bit-Cell Modeling

SAND2024-08549O PyTorch Circuit-Aware Bit-Cell Modeling, a Python library, demonstrates circuit-aware training for analog machine learning accelerators. Built upon PyTorch, this software provides hardware-aware versions of common neural network layers to mitigate non-ideal behavior from novel hardware. The software provides accurate forward and backward pass estimates for hardware-mapped neural networks that are implemented in crossbars (arrays) that contain a non-linear transistor selector device. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Bennett, Christopher↗
DOE OSTI2023

OLCF Summit Supercomputer GPU Snapshots During Double-Bit Errors and Normal Operations

As we move into the exascale era, the power and energy footprints of high-performance computing (HPC) systems have grown significantly larger. Due to the harsh power and thermal conditions the system, components are exposed to extreme operating conditions. Operation of such modern HPC systems requires deep insights into long term system behavior to maintain its efficiency as well as its longevity. To help the HPC community to gain such insights, we provide double-bit errors using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). The dataset relies on Nvidia XID records internally collected by GPU firmware at the time of failure occurrence, on the reboot-time logs of each Summit node, on node-level job scheduler records collected after each job termination, and on a 1Hz data rate from the baseboard management controllers (BMCs) of each Summit compute node using the OpenBMC event subscription protocol. Technical details can be found in the paper Oles et. al “Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study” ICS’24 (https://doi.org/10.1145/3650200.3656615).

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

XMark: Reliable Multi-Bit Watermarking for LLM-Generated Texts

Multi-bit watermarking has emerged as a promising solution for embedding imperceptible binary messages into Large Language Model (LLM)-generated text, enabling reliable attribution and tracing of malicious usage of LLMs. Despite recent progress, existing methods still face key limitations: some become computationally infeasible for large messages, while others suffer from a poor trade-off between text quality and decoding accuracy. Moreover, the decoding accuracy of existing methods drops significantly when the number of tokens in the generated text is limited, a condition that frequently arises in practical usage. To address these challenges, we propose XMark, a novel method for encoding and decoding binary messages in LLM-generated texts. The unique design of XMark’s encoder produces a less distorted logit distribution for watermarked token generation, preserving text quality, and also enables its tailored decoder to reliably recover the encoded message with limited tokens. Extensive experiments across diverse downstream tasks show that XMark significantly improves decoding accuracy while preserving the quality of watermarked text, outperforming prior methods. The code will be made publicly available upon acceptance.

Xu, Jiahao [University of Nevada, Reno]↗
DOE OSTI2020

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Chip Development Toward 12 bit 10 GSPS Cryogenic ADC for Multiplexed Quantum Readout

This presentation presents the background and plan for the development toward a 12 bit 10 GSPS cryogenic ADC for multiplexed quantum readout. It covers the first two chips that have been taped out and tested. It includes results for those chips and provides some context to plans for the upcoming chip tapeout and the final one to come later.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

The Atomic Drill Bit: Precision Controlled Atomic Fabrication of 2D Materials

The ability to deterministically fabricate nanoscale architectures with atomic precision is the central goal of nanotechnology, whereby highly localized changes in the atomic structure can be exploited to control device properties at their fundamental physical limit. Here, an automated, feedback-controlled atomic fabrication method is reported and the formation of 1D–2D heterostructures in MoS 2 is demonstrated through selective transformations along specific crystallographic orientations. The atomic-scale probe of an aberration-corrected scanning transmission electron microscope (STEM) is used, and the shape and symmetry of the scan pathway relative to the sample orientation are controlled. The focused and shaped electron beam is used to reliably create Mo 6 S 6 nanowire (MoS-NW) terminated metallic-semiconductor 1D–2D edge structures within a pristine MoS 2 monolayer with atomic precision. From these results, it is found that a triangular beam path aligned along the zig-zag sulfur terminated (ZZS) direction forms stable MoS-NW edge structures with the highest degree of fidelity without resulting in disordering of the surrounding MoS 2 monolayer. Density functional theory (DFT) calculations and ab initio molecular dynamic simulations (AIMD) are used to calculate the energetic barriers for the most stable atomic edge structures and atomic transformation pathways. These discoveries provide an automated method to improve understanding of atomic-scale transformations while opening a pathway toward more precise atomic-scale engineering of materials.

2D materials↗
DOE OSTI2024

Number of bits returned by a quantum estimation

We give two upper bounds to the mutual information in arbitrary quantum estimation strategies. The first is based on some simple Fourier properties of the estimation apparatus. The second is derived using the first, but, interestingly, depends only on the Fisher information of the parameter, so it is valid even beyond quantum estimation. We illustrate the usefulness of these bounds by characterizing the quantum phase estimation algorithm in the presence of noise. In addition, for the noiseless case, we extend the analysis beyond applying the bound and we discuss the optimal entangled and adaptive strategies, clarifying inaccuracies appearing on this topic in the literature.

97 MATHEMATICS AND COMPUTING↗