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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

Bit error protection in cache memories

A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Use of Rig Parameter Data in Bit Constraint Models for Improved Drilling Performance at The Geysers

Surface parameter measurements are routinely used during deep well construction to monitor and guide drilling conditions for improved performance and reduced costs. However, these measurements are of reduced value without a standard to aid in evaluation and decision making. A method is demonstrated whereby drill bit constraint models are used to interpret drilling response parameters. Drill rig parameter data for well GDC-36 at the Geysers Geothermal Field Power were acquired by Geysers Power Company and drilling contractor Kenai Drilling using Pason US DataHub and evaluated. Drilling parameters are evaluated using laboratory-validated rock reduction models for predicting the phenomenological response of drag bits (Detournay and Defourny, 1992) along with other model constraints in computational algorithms. The method is used to evaluate overall bit performance, monitor bit integrity, and detect the presence of drillstring vibrations and other conditions contributing to bit failure; comparisons are made to observations of bit wear and damage. The method will be applied in real-time to improve decision-making on subsequent wells and has applicability to development of advanced analytics on future geothermal wells using real-time electronic drilling recorder (EDR) data for improved performance and reduced drilling costs.

15 GEOTHERMAL ENERGY↗
DOE OSTI2021

Accelerating Binarized Neural Networks via Bit-Tensor-Cores in Turing GPUs

Despite foreseeing tremendous speedups over conventional deep neural networks, the performance advantage of binarized neural networks (BNNs) has merely been showcased on general-purpose processors such as CPUs and GPUs. In fact, due to being unable to leverage bit-level-parallelism with a word-based architecture, GPUs have been criticized for extremely low utilization (1%) when executing BNNs. Consequently, the latest tensorcores in NVIDIA Turing GPUs start to experimentally support bit computation. In this work, we look into this brand new bit computation capability and characterize its unique features. We show that the stride of memory access can significantly affect performance delivery and a data-format co-design is highly desired to support the tensorcores for achieving superior performance than existing software solutions without tensorcores. We realize the tensorcore-accelerated BNN design, particularly the major functions for fully-connect and convolution layers — bit matrix multiplication and bit convolution. Evaluations on two NVIDIA Turing GPUs show that, with ResNet-18, our BTC-BNN design can process ImageNet at a rate of 5.6K images per second, 77% faster than state-of-the-art. Our BNN approach is released on https://github.com/pnnl/TCBNN.

Li, Ang↗
DOE OSTI2019

BSTC: A Novel Binarized-Soft-Tensor-Core Design for Accelerating Bit-Based Approximated Neural Nets

Binarized neural network (or BNN) promises tremendous performance improvement over traditional DNNs through simplified bit-level computation and significantly reduced memory access/storage cost. In addition, it has other advantages of low-cost, low-energy and high-robustness, showing great utilization potential in resources-constrained, volatile and latency-critical applications, which are critical for future HPC execution. However, the promised significant performance gain of BNN inference has never been fully demonstrated on general-purpose processors, particularly on GPUs, due to: (i) the challenge to extract and leverage sufficient fine-grained bit-level-parallelism to saturate GPU cores when batch is small; (ii) the fundamental design conflict between bit-based BNN algorithm and underlying word-based architecture; (iii) architecture \& performance unfriendly BNN network design. To address (i) and (ii), we propose binarized-soft-tensor-core as a software-hardware codesign approach to construct bit-manipulation capability for modern GPUs to effectively harvest the emerging bit-level-parallelism. To tackle (iii), we propose intra- and inter-layer fusion techniques so that the entire BNN inference can be packed into a single GPU kernel, to avoid high-cost frequent launching. Experiments demonstrate that our design can achieve over 1000x speedup for raw inference latency and 10x for inference throughput over the state-of-the-art full-precision simulated BNN inference for AlexNet on ImageNet.

Li, Ang↗
DOE OSTI2021

ROP model for PDC bits in Geothermal drilling

Geothermal energy is a renewable source of energy, where heat extraction is preferentially balanced with the reservoir's natural heat recharge rate. The objective of this paper is to present and validate a novel rate of penetration (ROP) model for drilling hard and abrasive formations including granite formations for polycrystalline diamond compact (PDC) bits. The ROP model was developed based on a derived relationship of a threshold weight on cutter (WOC) and its corresponding depth of cut (DOC) for a single cutter. Laboratory data was used to scale the derived single cutter relationship to a full-hole ROP model for PDC bits. The ROP model includes a non-linear correlation for Phase I (inefficient drilling due to low WOB values) and a linear Phase II (efficient drilling) ROP response to WOB. The ROP model was verified using measured drilling parameter data from Utah FORGE well# 58-32 and data from Chocolate Mountains well # 17-8 in Southern California. When compared to oil and gas well drilling, geothermal drilling in granitic formations can be more difficult and complicated due to rock hardness and high temperatures. PDC bits can increase ROP and optimize drilling for these types of hard formations. This paper provides novel insight into the ROP response of PDC bits to drilling operational parameters.

15 GEOTHERMAL ENERGY↗
DOE OSTI2017

Corrosion behaviour of friction-bit-joined and weld-bonded AA7075-T6/galvannealed DP980

Joining of aluminium alloys 7075-T6 and galvannealed dual phase 980 steel was achieved by friction bit joining (FBJ) and weld-bonding (FBJ + adhesive) processes. Accelerated laboratory-scale corrosion tests were performed on both FBJ only and weld-bonded specimens to study joint strength under a corrosive environment. Static lap shear tests showed that both FBJ only and weld-bonded cases generally retained more than 80% of the joint strength of non-corroded specimens at the end of corrosion testing. The presence of Zn/Fe coating on the steel substrate resulted in improved corrosion resistance for FBJ specimens, compared to joints produced with bare steel. An optical microscopy was used for cross-sectional analysis of corroded specimens. Some corrosion on the joining bit was observed near the bit head. However, the joining bit was still intact on the steel substrate, indicating that the primary bond was sound.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Design of a readout circuit incorporating a 12-bit analog-to-digital converter for cooled infrared focal plane array

The infrared focal plane array (IRFPA) is gradually becoming more systematic. In order to enhance the signal processing capabilities, analog-to-digital converters (ADC) integrated into the readout integrated circuit (ROIC) is an important development trend. However, the cryogenic effects of MOSFET devices will affect the conversion accuracy of the ADC at 77 K. In this paper, the main parameters of MOSFET are extracted at 77 K in 0.18 μm CMOS process, and a cryogenic model is established. Based on this, a digital ROIC is designed, which integrates a 12-bit single-slope integral ADC in pixel unit. By applying continuous integral ramp generator and mixed-voltage comparator, a high-linearity and low-power consumption single-slope ADC is realized for the cooled readout circuit. The measured dynamic effective number of bits of the ADC at 77 K is 10.92 bits, the static no-missing code resolution reaches 11.99 bits, the maximum differential nonlinear |DNL| < 1LSB and maximum integral nonlinear |INL| < 1LSB. This paper realizes the design of a digital ROIC for IRFPA and improves the simulation accuracy at 77 K.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2021

A Modular Mechanism for Downhole Weight-on-Bit and Torque Reaction in Small Diameter Boreholes

Drilling systems that use downhole rotation must react torque either through the drill-string or near the motor to achieve effective drilling performance. Problems with drill-string loading such as buckling, friction, and twist become more severe as hole diameter decreases. Therefore, for small holes, reacting torque downhole without interfering with the application of weight-on-bit, is preferred. In this paper, we present a novel mechanism that enables effective and controllable downhole weight on bit transmission and torque reaction. This scalable design achieves its unique performance through four key features: (1) mechanical advantage based on geometry, (2) direction dependent behavior using rolling and sliding contact, (3) modular scalability by combining modules in series, and (4) torque reaction and weight on bit that are proportional to applied axial force. As a result, simple mechanical devices can be used to react large torques while allowing controlled force to be transmitted to the drill bit. We outline our design, provide theoretical predictions of performance, and validate the results using full-scale testing. The experimental results include laboratory studies as well as limited field testing using a percussive hammer. These results demonstrate effective torque reaction, axial force transmission, favorable scaling with multiple modules, and predictable performance that is proportional to applied force.

15 GEOTHERMAL ENERGY↗
DOE OSTI2014

Method to manufacture bit patterned magnetic recording media

A method to increase the storage density on magnetic recording media by physically separating the individual bits from each other with a non-magnetic medium (so-called bit patterned media). This allows the bits to be closely packed together without creating magnetic "cross-talk" between adjacent bits. In one embodiment, ferromagnetic particles are submerged in a resin solution, contained in a reservoir. The bottom of the reservoir is made of piezoelectric material.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Accelerating matrix-centric graph processing on GPUs through bit-level optimizations

Even though it is well known that binary values are common in graph applications (e.g., adjacency matrix), how to leverage the phenomenon for efficiency has not yet been adequately explored. This paper presents a systematic study on how to unlock the potential of the bit-level optimizations of graph computations that involve binary values. It proposes a two-level representation named Bit-Block Compressed Sparse Row (B2SR) and presents a series of optimizations to the graph operations on B2SR by the intrinsics of modern GPUs. It additionally introduces Deep Reinforcement Learning (DRL) as an efficient way to best configure the bit-level optimizations on the fly. Additionally, the DQN-based adaptive tile size selector with dedicated model training can reach 68% prediction accuracy. Evaluations on NVIDIA Pascal and Volta GPUs show that the optimizations bring up to 40× and 6555× for essential GraphBLAS kernels SpMV and SpGEMM, respectively, making GraphBLAS-based BFS accelerate up to 433×, SSSP, PR, and CC up to 35×, and TC up to 52×.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2020

Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation

In this paper, we studied the total ionization dose (TID) effects on the multilevel-cell (MLC) 3-D NAND flash memory using Co-60 gamma radiation. We found a significant page-to-page bit error variation within a physical memory block of the irradiated memory chip. Our analysis showed that the origin of the bit error variation is the unique vertical layer-dependent TID response of the 3-D NAND. We found that the memory pages located at the upper and lower layers of the 3-D stack show higher fails compared to the middle-layer pages of a given memory block. We confirmed our findings by comparing radiation response of four different chips of the same specification. In addition, we compared the TID response of the MLC 3-D NAND with that of the 2-D NAND chip, which showed less page-to-page variation in bit error within a given memory block. We discuss the possible application of our findings for the radiation-tolerant smart memory controller design.

3-D NAND flash↗
DOE OSTI2018

Bit threads in higher-curvature gravity

We generalize holographic bit threads to bulk theories with a gravitational action containing higher-curvature terms. Bit threads are a reformulation of holographic entanglement entropy, where the entropy is given by the maximum number of threads emanating from a boundary region into the bulk. We show that the addition of higher-curvature terms adds corrections to the bit thread thickness that depend on the local geometry and thread orientation. Two different methods are given: determination of the density bound by requiring the maximum number of threads through a given surface to reproduce the entanglement entropy functional on that surface, and application of Lagrange dualization. The results of the two methods are applied to Gauss-Bonnet gravity as the simplest non-trivial example.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Nonequilibrium formulation of varying-temperature bit erasure

Landauer's principle states that erasing a bit of information at fixed temperature T costs at least $k$ B $T$ ln 2 units of work. Here we investigate erasure at varying temperature, to which Landauer's result does not apply. Here we formulate bit erasure as a stochastic nonequilibrium process involving a compression of configuration space, with physical and logical states associated in a symmetric way. Erasure starts and ends at temperature T, but temperature can otherwise vary with time in an arbitrary way. Defined in this way, erasure is governed by a set of nonequilibrium fluctuation relations that show that varying-temperature erasure can done with less work than $k$ B $T$ ln 2. As a result, erasure and the complementary process of bit randomization can be combined to form a work-producing engine cycle.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Quantum bit threads

We give a bit thread prescription that is equivalent to the quantum extremal surface prescription for holographic entanglement entropy. Our proposal is inspired by considerations of bit threads in doubly holographic models, and equivalence is established by proving a generalisation of the Riemannian max-flow min-cut theorem. We explore our proposal’s properties and discuss ways in which islands and spacetime are emergent phenomena from the quantum bit thread perspective.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2021

Bit error protection in cache memories

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Kalamatianos, John↗
DOE OSTI2019

Towards a bit threads derivation of holographic entanglement of purification

We apply the bit thread formulation of holographic entanglement entropy to reduced states describing only the geometry contained within an entanglement wedge. We argue that a certain optimized bit thread configuration, which we construct, gives a purification of the reduced state to a full holographic state obeying a precise set of conditional mutual information relations. When this purification exists, we establish, under certain assumptions, the conjectured E P = E W relation equating the entanglement of purification with the area of the minimal cross section partitioning the bulk entanglement wedge. Along the way, we comment on minimal purifications of holographic states, geometric purifications, and black hole geometries.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Demonstration of photonic micro-ring resonator based digital bit magnitude comparator

This paper details the novel design, simulation and analysis of the digital photonic single-bit magnitude comparator with the utilization of silicon micro-ring resonator as its core component. The micro-ring resonator uses electro-optic carrier injection modulation properties with its ring waveguide being structured in PIN diode. Five micro-ring resonators are used in the proposed design, with each corresponds to the specific logic mode operation. This work also presents the time varying simulation, where two predetermined 1-bit input stream is injected into the circuit at the data rate of 1 Gbps, where its output is observed via oscilloscope, where results are obtained at the sampling rate of 1.6 THz. The timing diagram for the entire simulation is also shown together with additional results obtained from the simulation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2014

Bit patterned media optimization at 1 Tdot/in{sup 2} by post-annealing

We report on the fabrication of 1 Tdot/in{sup 2} bit patterned media with high coercivity (H{sub C}) and narrow intrinsic switching field distribution (iSFD) based on nanoimprint from a master pattern formed by e-beam guided block copolymer assembly onto a carbon hard mask and subsequent pattern transfer via etching into a thin CoCrPt perpendicular anisotropy recording layer. We demonstrate that an additional vacuum annealing step after pattern transfer into the CoCrPt layer and after Carbon hard mask removal not only yields recovery from undesired damage of the island edges, but actually transforms the islands into a magnetically more favorable compositional phase with higher H{sub C}, lower iSFD/H{sub C}, and three-fold increased thermal stability. Energy filtered transmission electron microscopy analysis reveals that the diffusion of Cr from the island cores to the periphery of the islands during post-annealing is responsible for the transformation of the magnetic bits into a more stable state.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗