Bump Bonding at JPL's MicroDevices Laboratory
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NASA Tech Briefs, December 2012
The topics include: Pattern Generator for Bench Test of Digital Boards; 670-GHz Down- and Up-Converting HEMT-Based Mixers; Lidar Electro-Optic Beam Switch with a Liquid Crystal Variable Retarder; Feedback Augmented Sub-Ranging (FASR) Quantizer; Real-Time Distributed Embedded Oscillator Operating Frequency Monitoring; Software Modules for the Proximity-1 Space Link Interleaved Time Synchronization (PITS) Protocol; Description and User Instructions for the Quaternion to Orbit v3 Software; AdapChem; Mars Relay Lander and Orbiter Overflight Profile Estimation; Extended Testability Analysis Tool; Interactive 3D Mars Visualization; Rapid Diagnostics of Onboard Sequences; MER Telemetry Processor; pyam: Python Implementation of YaM; Process for Patterning Indium for Bump Bonding; Archway for Radiation and Micrometeorite Occurrence Resistance; 4D Light Field Imaging System Using Programmable Aperture; Device and Container for Reheating and Sterilization; Radio Frequency Plasma Discharge Lamps for Use as Stable Calibration Light Sources; Membrane Shell Reflector Segment Antenna; High-Speed Transport of Fluid Drops and Solid Particles via Surface Acoustic Waves; Compact Autonomous Hemispheric Vision System; A Distributive, Non-Destructive, Real-Time Approach to Snowpack Monitoring; Wideband Single-Crystal Transducer for Bone Characterization; Numerical Simulation of Rocket Exhaust Interaction With Lunar Soil; Motion Imagery and Robotics Application (MIRA): Standards-Based Robotics; Particle Filtering for Model-Based Anomaly Detection in Sensor Networks; Ka-band Digitally Beamformed Airborne Radar Using SweepSAR Technique; Composite With In Situ Plenums; Multi-Beam Approach for Accelerating Alignment and Calibration of HyspIRI-Like Imaging Spectrometers; JWST Lifting System; Next-Generation Tumbleweed Rover; Pneumatic System for Concentration of Micrometer-Size Lunar Soil.
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Fabrication of Feedhorn-Coupled Transition Edge Sensor Arrays for Measurement of the Cosmic Microwave Background Polarization
Characterization of the minute cosmic microwave background (CMB) polarization signature requires multi-frequency high-throughput precision instrument systems. We have previously described the detector fabrication of a 40 gigahertz focal plane and now describe the fabrication of a 37-element dual-polarization detector module for measurement of the CMB at 90 gigahertz. The 72-TES (Transition Edge Sensor)-based bolometers in each module are coupled to a niobium-based planar orthomode transducer with integrated band defining filters implemented in microstrip transmission line. A single crystal silicon dielectric substrate serves as microstrip dielectric and as a thermal link between the membrane isolated MoAu TES operating at 150 millikelvins and the heat bath. A short silicon leg between the heat bath and the TES bolometer is designed for ballistic phonon transport and provides improved process control and uniformity of thermal conductance in the presence of phonon scattering on roughened surfaces. Micro-machined structures are used to realize the orthomode transducer backshort, provide out of band signal rejection, and a silicon photonic choke for feedhorn coupling are described. The backshort, choke wafer, and detector wafer are indium bump-bonded to create a single 37-element dual-polarization detector module. Fourteen such hexagonally shaped modules each 80 millimeters in size comprise two focal planes. These, along with the recently delivered 40 gigahertz focal plane, will survey a large fraction of the sky as part of the Johns Hopkins University-led ground-based CLASS (Cosmology Large Angular Scale Surveyor) telescope.
Detectors↗
Bump Bonding Using Metal-Coated Carbon Nanotubes
Bump bonding hybridization techniques use arrays of indium bumps to electrically and mechanically join two chips together. Surface-tension issues limit bump sizes to roughly as wide as they are high. Pitches are limited to 50 microns with bumps only 8-14 microns high on each wafer. A new process uses oriented carbon nanotubes (CNTs) with a metal (indium) in a wicking process using capillary actions to increase the aspect ratio and pitch density of the connections for bump bonding hybridizations. It merges the properties of the CNTs and the metal bumps, providing enhanced material performance parameters. By merging the bumps with narrow and long CNTs oriented in the vertical direction, higher aspect ratios can be obtained if the metal can be made to wick. Possible aspect ratios increase from 1:1 to 20:1 for most applications, and to 100:1 for some applications. Possible pitch density increases of a factor of 10 are possible. Standard capillary theory would not normally allow indium or most other metals to be drawn into the oriented CNTs, because they are non-wetting. However, capillary action can be induced through the ability to fabricate oriented CNT bundles to desired spacings, and the use of deposition techniques and temperature to control the size and mobility of the liquid metal streams and associated reservoirs. This hybridization of two technologies (indium bumps and CNTs) may also provide for some additional benefits such as improved thermal management and possible current density increases.
Lamb, James L.↗
Carbon Nanotube Bonding Strength Enhancement Using Metal "Wicking" Process
Carbon nanotubes grown from a surface typically have poor bonding strength at the interface. A process has been developed for adding a metal coat to the surface of carbon nano tubes (CNTs) through a wicking process, which could lead to an enhanced bonding strength at the interface. This process involves merging CNTs with indium as a bump-bonding enhancement. Classical capillary theory would not normally allow materials that do not wet carbon or graphite to be drawn into the spacings by capillary action because the contact angle is greater than 90 degrees. However, capillary action can be induced through JPL's ability to fabricate oriented CNT bundles to desired spacings, and through the use of deposition techniques and temperature to control the size and mobility of the liquid metal streams and associated reservoirs. A reflow and plasma cleaning process has also been developed and demonstrated to remove indium oxide, and to obtain smooth coatings on the CNT bundles.
Lamb, James L.↗
Optimization of Indium Bump Morphology for Improved Flip Chip Devices
Flip-chip hybridization, also known as bump bonding, is a packaging technique for microelectronic devices that directly connects an active element or detector to a substrate readout face-to-face, eliminating the need for wire bonding. In order to make conductive links between the two parts, a solder material is used between the bond pads on each side. Solder bumps, composed of indium metal, are typically deposited by thermal evaporation onto the active regions of the device and substrate. While indium bump technology has been a part of the electronic interconnect process field for many years and has been extensively employed in the infrared imager industry, obtaining a reliable, high-yield process for high-density patterns of bumps can be quite difficult. Under the right conditions, a moderate hydrogen plasma exposure can raise the temperature of the indium bump to the point where it can flow. This flow can result in a desirable shape where indium will efficiently wet the metal contact pad to provide good electrical contact to the underlying readout or imager circuit. However, it is extremely important to carefully control this process as the intensity of the hydrogen plasma treatment dramatically affects the indium bump morphology. To ensure the fine-tuning of this reflow process, it is necessary to have realtime feedback on the status of the bumps. With an appropriately placed viewport in a plasma chamber, one can image a small field (a square of approximately 5 millimeters on each side) of the bumps (10-20 microns in size) during the hydrogen plasma reflow process. By monitoring the shape of the bumps in real time using a video camera mounted to a telescoping 12 magnifying zoom lens and associated optical elements, an engineer can precisely determine when the reflow of the bumps has occurred, and can shut off the plasma before evaporation or de-wetting takes place.
Jones, Todd J.↗
Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays
The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.
Jhabvala, Murzy↗
Wafer-Level Membrane-Transfer Process for Fabricating MEMS
A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.
Yang, Eui-Hyeok↗
A 90 GHz Amplifier Assembled Using Flip-Chip Technology
This letter reports the performance of a novel single-stage W-band amplifier fabricated utilizing flip-chip bump-bonding. We have bump-bonded a high-speed, low-noise InP high electron mobility transistor (HEMT) device onto a separately fabricated passive circuit having a GaAs substrate.
FET amplifiers Millimeter wave FETs bump-bonding m↗
NASA Tech Briefs, April 2012
Topics include: Computational Ghost Imaging for Remote Sensing; Digital Architecture for a Trace Gas Sensor Platform; Dispersed Fringe Sensing Analysis - DFSA; Indium Tin Oxide Resistor-Based Nitric Oxide Microsensors; Gas Composition Sensing Using Carbon Nanotube Arrays; Sensor for Boundary Shear Stress in Fluid Flow; Model-Based Method for Sensor Validation; Qualification of Engineering Camera for Long-Duration Deep Space Missions; Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms; Bump Bonding Using Metal-Coated Carbon Nanotubes; In Situ Mosaic Brightness Correction; Simplex GPS and InSAR Inversion Software; Virtual Machine Language 2.1; Multi-Scale Three-Dimensional Variational Data Assimilation System for Coastal Ocean Prediction; Pandora Operation and Analysis Software; Fabrication of a Cryogenic Bias Filter for Ultrasensitive Focal Plane; Processing of Nanosensors Using a Sacrificial Template Approach; High-Temperature Shape Memory Polymers; Modular Flooring System; Non-Toxic, Low-Freezing, Drop-In Replacement Heat Transfer Fluids; Materials That Enhance Efficiency and Radiation Resistance of Solar Cells; Low-Cost, Rugged High-Vacuum System; Static Gas-Charging Plug; Floating Oil-Spill Containment Device; Stemless Ball Valve; Improving Balance Function Using Low Levels of Electrical Stimulation of the Balance Organs; Oxygen-Methane Thruster; Lunar Navigation Determination System - LaNDS; Launch Method for Kites in Low-Wind or No-Wind Conditions; Supercritical CO2 Cleaning System for Planetary Protection and Contamination Control Applications; Design and Performance of a Wideband Radio Telescope; Finite Element Models for Electron Beam Freeform Fabrication Process Autonomous Information Unit for Fine-Grain Data Access Control and Information Protection in a Net-Centric System; Vehicle Detection for RCTA/ANS (Autonomous Navigation System); Image Mapping and Visual Attention on the Sensory Ego-Sphere; HyDE Framework for Stochastic and Hybrid Model-Based Diagnosis; and IMAGESEER - IMAGEs for Education and Research.
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