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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS2020

Percussion Mechanism for the Mars2020 Coring Drill

The Mars2020 rover includes a Sampling & Caching Subsystem (SCS) that is required to acquire core samples of hard rocks and to abrade rocky surfaces flat and smooth in order to facilitate surface science. Hard, high strength rocks exhibit brittle failure modes, and can be drilled and chiseled efficiently using percussive impacts. The coring drill percussion mechanism was designed to provide those impacts with variable output force and to be used with various drill bits. A unique hammering mechanism, using a base-driven hammer, powered by a conventional rotary actuator driving a Scotch yoke, was designed to robustly provide the required function in a Martian environment for a life exceeding 2 million impacts.

Chrystal, Kyle↗
NASA NTRS2020

STIG: A Two-Speed Transmission Aboard the Mars2020 Coring Drill

The coring drill, part of the Sampling & Caching Subsystem (SCS) aboard the Mars2020 rover, demands a wide range of drill bit torque and speed capabilities during sample acquisition operations. The two driving operating points are high speed, low torque for rotary-percussive coring, as well as low speed, high torque for separating the rock core sample from its parent rock. The spindle twin-input transmission (STIG) allows these and other operating points to be reached with an actuator of substantially less peak power and maximum current draw than that of a single-speed actuator. Rather than containing gearing of its own, the transmission interfaces to an actuator with two outputs of different gear ratios, allowing the transmission to select one of the two of the outputs to be coupled to the drill bit. This paper describes the design, capabilities, and challenges associated with the transmission and the dual-output actuator.

Szwarc, Timothy↗
NASA NTRS2022

Testing Mars 2020 Flight Software and Hardware in the Surface System Development Environment

The Mars 2020 (M2020) Perseverance Rover is NASA's most advanced planetary rover mission to date. It includes a novel Sample Caching Subsystem (SCS) which will collect rock cores for possible future return to Earth, as well as an improved mobility system with enhanced autonomous navigation which will enable it to traverse faster and farther than prior rovers. The development of both systems required extensive flight software and flight hardware testing. To support this testing, we developed the Surface System Development Environment (SSDEV) and used it for a wide variety of testing. SSDEV is a bundled subset of M2020 Flight Software which runs on commercially available Linux computers and can be combined with multiple backend options for simulation and hardware control. The SSDEV architecture enabled our teams to perform much more testing of flight software and flight hardware than would have otherwise been possible. As a secondary benefit, the SSDEV-based test campaigns also helped our teams enter the operations phase of the mission with greater readiness of operations products and tools. In this paper, we summarize the motivation for SSDEV, provide an overview of the SSDEV architecture, list several examples of how SSDEV was used, and summarize lessons learned. SSDEV is not a substitute for integrated testing with flight-like avionics, but it enabled substantially more testing than would have otherwise been possible and also provided some unique benefits. We recommend architectures like SSDEV to future projects that need to perform extensive hardware and software testing using a limited set of flight-like avionics.

Wai, Dennis↗
NASA NTRS2022

Docking the Mars 2020 Perseverance Robotic Arm

The Mars 2020 Perseverance Rover includes an innovative Sample Caching Subsystem (SCS). Two key features of SCS are the ability to collect and process rock and regolith samples for possible future return to Earth and the ability to switch between different types of drill bits for coring rocks, abrading rocks, and collecting regolith. These capabilities are enabled by a Corer mounted on the end of a Robotic Arm and a Bit Carousel mounted on the front of the rover body. Beneath the Bit Carousel, a smaller Sample Handling Arm can insert and remove sample tubes from sampling bits in the carousel. For the Corer to interface with the Bit Carousel so that it can exchange drill bits and hand off rock samples, the Robotic Arm must maneuver the Corer to dock with the Bit Carousel. Docking serves two primary purposes: it precisely aligns the Corer with the hardware inside the Bit Carousel, and it applies enough preload between the Corer and the Bit Carousel to make them stay aligned through the process of bit exchange.The docking assembly consists of four concave alignment cones mounted on a large rotating ring, through the center of which the drill can exchange bits and samples with the Bit Carousel. The coring drill includes four alignment posts which mate with the four cones on the dock. Docking uses an algorithm we call “Force-Corrected Docking”, which means it iteratively reads the force/moments reported by the FTS, performs a small motion to reduce sideload and moments while increasing preload, and repeats until reaching a deadband around the target preload. Because docking is a critical function for SCS, the dock hardware and algorithm have been tested thousands of times over 7 years in various stages of development. The culmination of this work is a reliable docking system which has been demonstrated and used in flight.

Warner, Antonia↗
NASA NTRS1993

Analysis of cache for streaming tape drive

A tape subsystem consists of a controller and a tape drive. Tapes are used for backup, data interchange, and software distribution. The backup operation is addressed. During a backup operation, data is read from disk, processed in CPU, and then sent to tape. The processing speeds of a disk subsystem, CPU, and a tape subsystem are likely to be different. A powerful CPU can read data from a fast disk, process it, and supply the data to the tape subsystem at a faster rate than the tape subsystem can handle. On the other hand, a slow disk drive and a slow CPU may not be able to supply data fast enough to keep a tape drive busy all the time. The backup process may supply data to tape drive in bursts. Each burst may be followed by an idle period. Depending on the nature of the file distribution in the disk, the input stream to the tape subsystem may vary significantly during backup. To compensate for these differences and optimize the utilization of a tape subsystem, a cache or buffer is introduced in the tape controller. Most of the tape drives today are streaming tape drives. A streaming tape drive goes into reposition when there is no data from the controller. Once the drive goes into reposition, the controller can receive data, but it cannot supply data to the tape drive until the drive completes its reposition. A controller can also receive data from the host and send data to the tape drive at the same time. The relationship of cache size, host transfer rate, drive transfer rate, reposition, and ramp up times for optimal performance of the tape subsystem are investigated. Formulas developed will also show the advantages of cache watermarks to increase the streaming time of the tape drive, maximum loss due to insufficient cache, tradeoffs between cache and reposition times and the effectiveness of cache on a streaming tape drive due to idle times or interruptions due in host transfers. Several mathematical formulas are developed to predict the performance of the tape drive. Some examples are given illustrating the usefulness of these formulas. Finally, a summary and some conclusions are provided.

Chinnaswamy, V.↗
NASA NTRS2012

Sample Sealing Approaches for Mars Sample Return Caching

Objective ot this project was to investigate sealing methods for encapsulating samples in 1 cm diameter thin-walled sample tubes applicable to future proposed Mars Sample Return Techniques implemented include a spring energized Teflon sleeve plug, a crimped tube seal, a heat-activated shape memory alloy plug, a shape memory alloy activated cap, a solder-based plug, and a solder-based cap

Mars Sample Return (MSR) mission↗
DOE OSTI2016

Milestone Report - Level-2 Milestone 5589: Modernization and Expansion of LLNL Archive Disk Cache

This report documents Livermore Computing (LC) activities in support of ASC L2 milestone 5589: Modernization and Expansion of LLNL Archive Disk Cache, due March 31, 2016. The full text of the milestone is included in Attachment 1. The description of the milestone is: Description: Configuration of archival disk cache systems will be modernized to reduce fragmentation, and new, higher capacity disk subsystems will be deployed. This will enhance archival disk cache capability for ASC archive users, enabling files written to the archives to remain resident on disk for many (6–12) months, regardless of file size. The milestone was completed in three phases. On August 26, 2015 subsystems with 6PB of disk cache were deployed for production use in LLNL’s unclassified HPSS environment. Following that, on September 23, 2015 subsystems with 9 PB of disk cache were deployed for production use in LLNL’s classified HPSS environment. On January 31, 2016, the milestone was fully satisfied when the legacy Data Direct Networks (DDN) archive disk cache subsystems were fully retired from production use in both LLNL’s unclassified and classified HPSS environments, and only the newly deployed systems were in use.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1991

Formal verification of an MMU and MMU cache

We describe the formal verification of a hardware subsystem consisting of a memory management unit and a cache. These devices are verified independently and then shown to interact correctly when composed. The MMU authorizes memory requests and translates virtual addresses to real addresses. The cache improves performance by maintaining a LRU (least recently used) list from the memory resident segment table.

Schubert, E. T.↗
NASA NTRS1986

The Science of Computing: Virtual Memory

In the March-April issue, I described how a computer's storage system is organized as a hierarchy consisting of cache, main memory, and secondary memory (e.g., disk). The cache and main memory form a subsystem that functions like main memory but attains speeds approaching cache. What happens if a program and its data are too large for the main memory? This is not a frivolous question. Every generation of computer users has been frustrated by insufficient memory. A new line of computers may have sufficient storage for the computations of its predecessor, but new programs will soon exhaust its capacity. In 1960, a longrange planning committee at MIT dared to dream of a computer with 1 million words of main memory. In 1985, the Cray-2 was delivered with 256 million words. Computational physicists dream of computers with 1 billion words. Computer architects have done an outstanding job of enlarging main memories yet they have never kept up with demand. Only the shortsighted believe they can.

Denning, Peter J.↗
NASA NTRS2009

Planetary Sample Caching System Design Options

Potential Mars Sample Return missions would aspire to collect small core and regolith samples using a rover with a sample acquisition tool and sample caching system. Samples would need to be stored in individual sealed tubes in a canister that could be transfered to a Mars ascent vehicle and returned to Earth. A sample handling, encapsulation and containerization system (SHEC) has been developed as part of an integrated system for acquiring and storing core samples for application to future potential MSR and other potential sample return missions. Requirements and design options for the SHEC system were studied and a recommended design concept developed. Two families of solutions were explored: 1)transfer of a raw sample from the tool to the SHEC subsystem and 2)transfer of a tube containing the sample to the SHEC subsystem. The recommended design utilizes sample tool bit change out as the mechanism for transferring tubes to and samples in tubes from the tool. The SHEC subsystem design, called the Bit Changeout Caching(BiCC) design, is intended for operations on a MER class rover.

MSR↗
DOE OSTI2016

Using Formal Grammars to Predict I/O Behaviors in HPC: The Omnisc'IO Approach

The increasing gap between the computation performance of post-petascale machines and the performance of their I/O subsystem has motivated many I/O optimizations including prefetching, caching, and scheduling. In order to further improve these techniques, modeling and predicting spatial and temporal I/O patterns of HPC applications as they run has become crucial. In this paper we present Omnisc'IO, an approach that builds a grammar-based model of the I/O behavior of HPC applications and uses it to predict when future I/O operations will occur, and where and how much data will be accessed. To infer grammars, Omnisc'IO is based on StarSequitur, a novel algorithm extending Nevill-Manning's Sequitur algorithm. Omnisc'IO is transparently integrated into the POSIX and MPI I/O stacks and does not require any modification in applications or higher-level I/O libraries. It works without any prior knowledge of the application and converges to accurate predictions of any N future I/O operations within a couple of iterations. Its implementation is efficient in both computation time and memory footprint.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

PIMS: A Lightweight Processing-in-Memory Accelerator for Stencil Computations

Stencil computation is a classic computational kernel present in many high-performance scientific applications, like image process- ing and partial differential equation solvers (PDE). A stencil compu- tation sweeps over a multi-dimensional grid and repeatedly updates values associated with points using the values from neighboring points. Stencil computations often employ large datasets that ex- ceed cache capacity, leading to excessive accesses to the memory subsystem. As such, 3D stencil computations on large grid sizes are memory-bound. In this paper we present PIMS, an in-memory accelerator for stencil computations. PIMS, implemented in the logic layer of a 3D- stacked memory, exploits the high bandwidth provided by through- silicon vias to reduce redundant memory traffic. Our comprehensive evaluation using three different grid sizes with six categories of orders indicate that the proposed architecture reduces 48.25% of data movement on average and obtains up to 65.55% of bank conflict reduction.

Li, Jie↗
DOE OSTI2018

Sparse Matrix-Matrix Multiplication on Multilevel Memory Architectures: Algorithms and Experiments

Architectures with multiple classes of memory media are becoming a common part of mainstream supercomputer deployments. So called multi-level memories offer differing characteristics for each memory component including variation in bandwidth, latency and capacity. This paper investigates the performance of sparse matrix multiplication kernels on two leading highperformance computing architectures — Intel's Knights Landing processor and NVIDIA's Pascal GPU. We describe a data placement method and a chunking-based algorithm for our kernels that exploits the existence of the multiple memory spaces in each hardware platform. We evaluate the performance of these methods w.r.t. standard algorithms using the auto-caching mechanisms Our results show that standard algorithms that exploit cache reuse performed as well as multi-memory-aware algorithms for architectures such as Ki\iLs where the memory subsystems have similar latencies. However, for architectures such as GPUS where memory subsystems differ significantly in both bandwidth and latency, multi-memory-aware methods are crucial for good performance. In addition, our new approaches permit the user to run problems that require larger capacities than the fastest memory of each compute node without depending on the software-managed cache mechanisms.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2012

Mars Technology Rover with Arm-Mounted Percussive Coring Tool, Microimager, and Sample-Handling Encapsulation Containerization Subsystem

A report describes the PLuto (programmable logic) Mars Technology Rover, a mid-sized FIDO (field integrated design and operations) class rover with six fully drivable and steerable cleated wheels, a rocker-bogey suspension, a pan-tilt mast with panorama and navigation stereo camera pairs, forward and rear stereo hazcam pairs, internal avionics with motor drivers and CPU, and a 5-degrees-of-freedom robotic arm. The technology rover was integrated with an arm-mounted percussive coring tool, microimager, and sample handling encapsulation containerization subsystem (SHEC). The turret of the arm contains a percussive coring drill and microimager. The SHEC sample caching system mounted to the rover body contains coring bits, sample tubes, and sample plugs. The coring activities performed in the field provide valuable data on drilling conditions for NASA tasks developing and studying coring technology. Caching of samples using the SHEC system provide insight to NASA tasks investigating techniques to store core samples in the future.

Younse, Paulo J.↗
NASA NTRS2008

Initial Performance Results on IBM POWER6

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Saini, Subbash↗
NASA NTRSDate not supplied

The Mars 2020 Watson Imaging Subsystem of the Sherloc Investigation and Anticpated Early Results

In February 2021, the Mars 2020 Perseverance rover is anticipated to touch down in Jezero crater, Mars. Perseverance is unique in that it will conduct in situ science as well as cache samples for eventual return to Earth for analysis in terrestrial laboratories. It will explore the geologic setting within Jezero over a range of scales in order to address fundamental questions about the evolution of Mars and assess whether there is evidence of past or present Martian life. The Wide Angle Topographic Sensor for Operations and eNgineering (WATSON), one of two imaging subsystems within the Scanning Habitable Environments with Raman and Luminescence for Organics and Chemicals (SHERLOC) instrument[1,2], acquires images that support scientific study of Jezero crater and sample acquisition, as well as rover and instrument operations(Fig. 1).WATSON serves a number of roles; it 1) provides color context imaging of SHERLOC and Planetary Instrument for X-Ray Litho chemistry (PIXL)analysis locations, placing the spatial distribution of organics and mineralogy detected by SHERLOC and the elemental maps generated by PIXL within the context of rock texture and structure; 2)acquires stand-alone observations of rock structures and textures from the outcrop to the grain scale; and 3)images rover components and other instruments to monitor their health and condition. We plan to present images acquired within the first ~30 sols of operations.

M E Minitti↗
NASA NTRS2018

Auto-Gopher-2 – An Autonomous Wireline Rotary Piezo-Percussive Deep Drilling Mechanism

Drilling deep into the subsurface of planetary bodies in the Solar System for samples acquisition enables critical capabilities for future NASA exploration missions in its quest to understand the origins of the Solar System and potentially the search for life. Such planetary bodies as Mars and Europa are key targets for potential missions that would require reaching great depths. Performing drilling while using minimal mass/volume systems and with low energy consumption are the main requirements that are imposed on such technologies. A wireline deep drill, called Auto-Gopher-2, is currently being developed as a joint effort between JPL and Honeybee Robotics Ltd. The Auto-Gopher II is a wireline rotary piezo-percussive deep drilling mechanism that combines formation breaking by rotating and piezoelectric actuator hammering and cuttings removal by rotating a fluted bit. The hammering mechanism is based on the Ultrasonic/Sonic Drill/Corer (USDC) mechanism that has been developed as an adaptable tool for many drilling and coring applications. The USDC uses an intermediate ball-shape free-mass to transform high frequency vibrations of a piezoelectric transducer horn tip into sonic hammering of the drill bit. The lessons learned from the previous studies are being implemented into the development of the Auto-Gopher-II, an autonomous deep wireline drill with integrated cuttings and sample management and drive electronics. Subsystems of the wireline drill are being developed in parallel at JPL and Honeybee Robotics, Ltd. Issues related to the bit and its ability to retain the cuttings for caching and removal are currently being addressed. This paper presents the development efforts of the piezoelectric actuator, cuttings removal and retention flutes and drive electronics.

Bar-Cohen, Yoseph↗
NASA NTRS2021

Development of the Sample Fetch Rover Locomotion Subsystem

A novel system for planetary surface mobility is being designed in response to the challenging requirements of the Sample Fetch Rover (SFR) mission, part of the NASA/ESA Mars Sample Return campaign (MSR). The rover will retrieve tubes with rock and soil samples, previously acquired and cached by NASA’s Perseverance rover in depots on the Martian surface. SFR will have to acquire, transport and deliver the tubes to a lander in a tight time window. This will require significant mobility capabilities, unprecedented for Mars rovers. The highly time-constrained traverse needs, together with the strictly limited mass and volume imposed by the accommodation on the lander, have pushed the design of the SFR locomotion to seek innovative solutions. In response to that, a four-wheel drive system is being developed, integrated with a deployable pitch-averaging suspension. This will be the first time that four-wheel locomotion is used on Mars and on robotic planetary rovers in general. The system, relying on high-efficiency drive actuators designed to operate in Mars environment, shows potential for terrain and obstacle negotiation performance comparable with that of larger vehicles. The implementation also takes advantage of the superelastic Spring-Tyre technology currently being developed by NASA Glenn Research Center, which, thanks to its traction and obstacle compliance properties, will allow SFR to navigate difficult ground and achieve its mission objectives.

Rehmatullah, Faizan↗