Synthesis of current-switching circuits with cell matching using p-n-p and n-p-n transistors
Logical circuit for analysis of switching circuits with cell matching using p-n-p and n-p-n transistors
TRANSISTOR↗
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On-chip evolutionary synthesis of reconfigurable analog computing circuits
The paper presents a Field Programmable Transistor Array (FPTA), developed as an experimental platform for implementing flexible, reconfigurable analog computing.
FPTA reconfigurable chips evolvable hardware↗
Experiments on the evolution of digital to analog converters
Currently, there is a research effort in Evolvable Hardware being driven towards two purposes: the synthesis of circuits of medium to high complexity; and the design of reconfigurable architectures that facilitate the system evolvability and on-chip implementation of the evolved circuits. This work addresses these issues by describing the evolution of Digital to Analog Converters (DACs).
DACs evolvable hardware hierarchical evolution gen↗
Development of siloxane-containing epoxy polymers for electrical circuit embedment applications
Synthesis of epoxy polymers containing siloxane linkage
Patterson, W. J.↗
The general transfer matrix for networks with open-circuited or short-circuited stubs.
Analysis and synthesis of distributed transmission line networks with open or short circuited shunts or series stubs, describing composite transfer matrices
Griffin, J. R.↗
Experiments on technology mapping using different cell libraries
Technology mapping is one of the major steps in the synthesis process of integrated circuits. Efficient algorithms have been proposed in the recent past to optimize the number of cells required to implement a given design, but not enough effort has been spent in studying the relationship between the quality of the circuit produced by the logic synthesis tool and the cell library used to perform the mapping. In this paper we present experiments on technology mapping that show how the design of the cell library can influence the area and the delay of the synthesized circuit.
Macii, Enrico↗
Generalized tree circuit - the basic building block of an extended decomposition theory.
Algorithm for synthesis of switching circuit in generaized tree circuit form
SWITCHING CIRCUIT↗
Evolutionary design of smart analog circuits
This paper discusses the use of Evolvable Hardware (EHW) in automatic synthesis of electronic circuits for computational intelligence (CI) hardware.
evolvable hardware fuzzy logic reconfigurable devi↗
Evolving electronic circuits for computational intelligence hardware
This paper discusses the use of Evolvable Hardware (EHW) in automatic synthesis of electronic circuits for computational intelligence (CI) hardware.
evolvable hardware fuzzy neurons FPTA↗
Evolution of CMOS Circuits in Simulations and Directly in Hardware on a Programmable Chip
The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA).
evolvable hardware reconfigurable hardware genetic↗
Synthesis of low frequency transfer functions with microelectronic circuits.
LF transfer functions synthesized with microelectronic circuits
NETWORK SYNTHESIS↗
On Polymorphic Circuits and Their Design Using Evolutionary Algorithms
This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality. A function change does not require switches/reconfiguration as in traditional approaches. Instead the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained by evolutionary design/evolvable hardware techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines, know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any arrangement (in simulations only). The second mode uses a Field Programmable Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable architecture (these experiments are performed both in simulations and on FPTA chips). The experiments demonstrated the synthesis. of polytronic circuits by evolution. The capacity of storing/hiding "extra" functions provides for watermark/invisible functionality, thus polytronics may find uses in intelligence/security applications.
Stoica, Adrian↗
Faster Evolution of More Multifunctional Logic Circuits
A modification in a method of automated evolutionary synthesis of voltage-controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six-function circuit in less than half an hour. The concepts of automated evolutionary synthesis and voltage-controlled multifunctional logic circuits were described in a number of prior NASA Tech Briefs articles. To recapitulate: A circuit is designed to perform one of several different logic functions, depending on the value of an applied control voltage. The circuit design is synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. In this process, random populations of integer strings that encode electronic circuits play a role analogous to that of chromosomes. An evolved circuit is tested by computational simulation (prior to testing in real hardware to verify a final design). Then, in a fitness-evaluation step, responses of the circuit are compared with specifications of target responses and circuits are ranked according to how close they come to satisfying specifications. The results of the evaluation provide guidance for refining designs through further iteration.
Stoica, Adrian↗
A programable display synthesizing system for man machine communications research
Flight control display cockpit simulators - synthesis by closed circuit television
Hatfield, J. J.↗
Knowledge representation to support reasoning based on multiple models
Model Based Reasoning is a powerful tool used to design and analyze systems, which are often composed of numerous interactive, interrelated subsystems. Models of the subsystems are written independently and may be used together while they are still under development. Thus the models are not static. They evolve as information becomes obsolete, as improved artifact descriptions are developed, and as system capabilities change. Researchers are using three methods to support knowledge/data base growth, to track the model evolution, and to handle knowledge from diverse domains. First, the representation methodology is based on having pools, or types, of knowledge from which each model is constructed. In addition information is explicit. This includes the interactions between components, the description of the artifact structure, and the constraints and limitations of the models. The third principle we have followed is the separation of the data and knowledge from the inferencing and equation solving mechanisms. This methodology is used in two distinct knowledge-based systems: one for the design of space systems and another for the synthesis of VLSI circuits. It has facilitated the growth and evolution of our models, made accountability of results explicit, and provided credibility for the user community. These capabilities have been implemented and are being used in actual design projects.
Gillam, April↗
ProperCAD: A portable object-oriented parallel environment for VLSI CAD
Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.
Ramkumar, Balkrishna↗
EHWPACK: An evolvable hardware environment using the SPICE simulator and the Field Programmable Transistor Array
This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.
evolvable hardware spice simulations↗
Automatic hardware synthesis
The complexity of the circuit that can fit on an integrated circuit (IC) chip has reached the level of a million transistors with the advent of Very-Large-Scale Integration (VLSI). Several automatic synthesis systems have evolved that 'aid' the human designer in managing this complexity. This paper surveys such efforts. The synthesis is viewed as the process of transforming a high-level design specification into a lower level design specification that includes more structural details, leading to the physical design of the IC. The characteristics of ten automatic synthesis systems are summarized.
Shiva, S. G.↗