A temporary synchronous clock source for spinning spacecraft
Breadboard model of spaceborne synchronous clock pulse generator for spinning spacecraft
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Optimal Estimation of Clock Values and Trends from Finite Data
We show how to solve two problems of optimal linear estimation from a finite set of phase data. Clock noise is modeled as a stochastic process with stationary dth increments. The covariance properties of such a process are contained in the generalized autocovariance function (GACV). We set up two principles for optimal estimation: with the help of the GACV, these principles lead to a set of linear equations for the regression coefficients and some auxiliary parameters. The mean square errors of the estimators are easily calculated. The method can be used to check the results of other methods and to find good suboptimal estimators based on a small subset of the available data.
stationary increments↗
Ground control system for the midcourse space experiment UTC clock
One goal of the Midcourse Space Experiment (MSX) spacecraft Operations Planning Center is to maintain the onboard satellite UTC clock (UTC(MSX)) to within 1 millisecond of UTC(APL) (the program requirement is 10 msec). The UTC(MSX) clock employs as its time base an APL built 5 MHz quartz oscillator, which is expected to have frequency instabilities (aging rate + drift rate + frequency offset) that will cause the clock to drift approximately two to ten milliseconds per day. The UTC(MSX) clock can be advanced or retarded by the APL MSX satellite ground control center by integer multiples of 1 millisecond. The MSX Operations Planning Center is developing software which records the drift of UTC(MSX) relative to UTC(APL) and which schedules the time of day and magnitude of UTC(MSX) clock updates up to 48 hours in advance. Because of the manner in which MSX spacecraft activities are scheduled, MSX clock updates are planned 24 to 48 hours in advance, and stored in the satellite's computer controller for later execution. Data will be collected on the drift of UTC(MSX) relative to UTC(APL) over a three to five day period. Approximately six times per day, the time offset between UTC(MSX) and UTC(APL) will be measured by APL with a resolution of less than 100 microseconds. From this data a second order analytical model of the clock's drift will be derived. This model will be used to extrapolate the offset of the MSX clock in time from the present to 48 hours in the future. MSX clock updates will be placed on the spacecraft's daily schedule whenever the predicted clock offset exceeds 0.5 milliseconds. The paper includes a discussion of how the empirical model of the MSX clock is derived from satellite telemetry data, as well as the algorithm used to schedule MSX clock updates based on the model.
Dragonette, Richard↗
Optimal Prediction of Clocks from Finite Data
This talk is about optimal linear prediction of processes with stationary dth increments, which serve as a class of models for random clock disturbances. The predictor is obtained by orthogonal projection on the affine space of estimators whose errors are invariant to additive polynomials of degree < d. The projection conditions give a system of linear equations thatcan be solved straightforwardly for the regression coefficients. If the data are equally spaced, then the predictor can be obtained by an extension of Levinson's algorithm.
stationary increments↗
Model Checking a Self-Stabilizing Distributed Clock Synchronization Protocol for Arbitrary Digraphs
This report presents the mechanical verification of a self-stabilizing distributed clock synchronization protocol for arbitrary digraphs in the absence of faults. This protocol does not rely on assumptions about the initial state of the system, other than the presence of at least one node, and no central clock or a centrally generated signal, pulse, or message is used. The system under study is an arbitrary, non-partitioned digraph ranging from fully connected to 1-connected networks of nodes while allowing for differences in the network elements. Nodes are anonymous, i.e., they do not have unique identities. There is no theoretical limit on the maximum number of participating nodes. The only constraint on the behavior of the node is that the interactions with other nodes are restricted to defined links and interfaces. This protocol deterministically converges within a time bound that is a linear function of the self-stabilization period.
Malekpour, Mahyar R.↗
Model Checking a Byzantine-Fault-Tolerant Self-Stabilizing Protocol for Distributed Clock Synchronization Systems
This report presents the mechanical verification of a simplified model of a rapid Byzantine-fault-tolerant self-stabilizing protocol for distributed clock synchronization systems. This protocol does not rely on any assumptions about the initial state of the system. This protocol tolerates bursts of transient failures, and deterministically converges within a time bound that is a linear function of the self-stabilization period. A simplified model of the protocol is verified using the Symbolic Model Verifier (SMV) [SMV]. The system under study consists of 4 nodes, where at most one of the nodes is assumed to be Byzantine faulty. The model checking effort is focused on verifying correctness of the simplified model of the protocol in the presence of a permanent Byzantine fault as well as confirmation of claims of determinism and linear convergence with respect to the self-stabilization period. Although model checking results of the simplified model of the protocol confirm the theoretical predictions, these results do not necessarily confirm that the protocol solves the general case of this problem. Modeling challenges of the protocol and the system are addressed. A number of abstractions are utilized in order to reduce the state space. Also, additional innovative state space reduction techniques are introduced that can be used in future verification efforts applied to this and other protocols.
Malekpour, Mahyar R.↗
Mercury Atomic Frequency Standards for Space Based Navigation and Timekeeping
A low power Mercury Atomic Frequency Standard (MAFS) has been developed and demonstrated on the path towards future space clock applications. A self contained mercury ion breadboard clock: emulating flight clock interfaces, steering a USO local oscillator, and consuming approx 40 Watts has been operating at JPL for more than a year. This complete, modular ion clock instrument demonstrates that key GNSS size, weight, and power (SWaP) requirements can be achieved while still maintaining short and long term performance demonstrated in previous ground ion clocks. The MAFS breadboard serves as a flexible platform for optimizing further space clock development and guides engineering model design trades towards fabrication of an ion clock for space flight.
Global Positioning Systems (GPS)↗
Design and Performance Analysis of a Massively Parallel Atmospheric General Circulation Model
In the 1990's computer manufacturers are increasingly turning to the development of parallel processor machines to meet the high performance needs of their customers. Simultaneously, atmospheric scientists study weather and climate phenomena ranging from hurricanes to El Nino to global warming that require increasingly fine resolution models. Here, implementation of a parallel atmospheric general circulation model (GCM) which exploits the power of massively parallel machines is described. Using the horizontal data domain decomposition methodology, this FORTRAN 90 model is able to integrate a 0.6 deg. longitude by 0.5 deg. latitude problem at a rate of 19 Gigaflops on 512 processors of a Cray T3E 600; corresponding to 280 seconds of wall-clock time per simulated model day. At this resolution, the model has 64 times as many degrees of freedom and performs 400 times as many floating point operations per simulated day as the model it replaces.
Schaffer, Daniel S.↗
RH1020 Single Event Clock Upset Summary Report
This report summarizes the testing and analysis of "single event clock upset' in the RH1020. Also included are SEU-rate predictions and design recommendations for risk analysis and reduction. The subject of "upsets" in the RH1020 is best understood by using a model consisting of a global clock buffer and a D-type flip-flop as the basic memory unit. The RH1020 is built on the ACT 1 family architecture. As such, it has one low-skew global clock buffer with a TTL-level input threshold that is accessed via a single dedicated pin. The clock signal is driven to full CMOS levels, buffered, and sent to individual row buffers with one buffer per channel. For low-skew performance, the outputs of all of the RH1020 row buffers are shorted together via metal lines, as is done in the A1020B. All storage in the RH1020 consists of routed flip-flops, constructed with multiplexors and feedback through the routing segments. A simple latch can be constructed from a single (combinatorial or C) module; an edge-triggered flip-flop is constructed using two concatenated latches. There is no storage in the I/O modules. The front end of the clock buffering circuitry, at a common point relative to the row buffer, is a sub-circuit that was determined to be the most susceptible to heavy ions. This is due, in part, to its smaller transistors compared to the rest of the circuitry. This conclusion is also supported by SPICE simulations and an analysis of the heavy ion data, described in this report. The edge triggered D flip-flop has two single-event-upset modes. Mode one, called C-module upset, is caused by a heavy ion striking the C-module's sensitive area on the silicon and produces a soft single bit error at the output of the flip-flop. Mode two, called clock upset, is caused by a heavy ion strike on the clock buffer, generating a runt pulse interpreted as a false clock signal and consequently producing errors at the flip-flop outputs. C-module upset sensitivity in the RH1020 is essentially the same as that of its ACT 1 siblings (A1020, A1020A and A1020B), which were well tested, analyzed, and documented in the literature.
Katz, Richard B.↗
A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol
In this paper we present a formal model of asynchronous communication as a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into the signal stream consumed by an independently clocked processor. This transformation 'blurs' edges and 'dilates' time due to differences in the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on asynchronous communications at ISO protocol level 1 (physical level). We develop part of the reusable formal theory that permits the convenient application of the model. We use the theory to show that a biphase mark protocol can be used to send messages of arbitrary length between two asynchronous processors. We study two versions of the protocol, a conventional one which uses cells of size 32 cycles and an unconventional one which uses cells of size 18. We conjecture that the protocol can be proved to work under our model for smaller cell sizes and more divergent clock rates but the proofs would be harder.
Moore, J. Strother↗
Using Integer Clocks to Verify the Timing-Sync Sensor Network Protocol
We use the UPPAAL model checker for Timed Automata to verify the Timing-Sync time-synchronization protocol for sensor networks (TPSN). The TPSN protocol seeks to provide network-wide synchronization of the distributed clocks in a sensor network. Clock-synchronization algorithms for sensor networks such as TPSN must be able to perform arithmetic on clock values to calculate clock drift and network propagation delays. They must be able to read the value of a local clock and assign it to another local clock. Such operations are not directly supported by the theory of Timed Automata. To overcome this formal-modeling obstacle, we augment the UPPAAL specification language with the integer clock derived type. Integer clocks, which are essentially integer variables that are periodically incremented by a global pulse generator, greatly facilitate the encoding of the operations required to synchronize clocks as in the TPSN protocol. With this integer-clock-based model of TPSN in hand, we use UPPAAL to verify that the protocol achieves network-wide time synchronization and is devoid of deadlock. We also use the UPPAAL Tracer tool to illustrate how integer clocks can be used to capture clock drift and resynchronization during protocol execution
Huang, Xiaowan↗
Observation model and parameter partials for the JPL geodetic GPS modeling software GPSOMC
The physical models employed in GPSOMC and the modeling module of the GIPSY software system developed at JPL for analysis of geodetic Global Positioning Satellite (GPS) measurements are described. Details of the various contributions to range and phase observables are given, as well as the partial derivatives of the observed quantities with respect to model parameters. A glossary of parameters is provided to enable persons doing data analysis to identify quantities in the current report with their counterparts in the computer programs. There are no basic model revisions, with the exceptions of an improved ocean loading model and some new options for handling clock parametrization. Such misprints as were discovered were corrected. Further revisions include modeling improvements and assurances that the model description is in accord with the current software.
Sovers, O. J.↗
Dynamic modelling and estimation of the error due to asynchronism in a redundant asynchronous multiprocessor system
The use of Redundant Asynchronous Multiprocessor System to achieve ultrareliable Fault Tolerant Control Systems shows great promise. The development has been hampered by the inability to determine whether differences in the outputs of redundant CPU's are due to failures or to accrued error built up by slight differences in CPU clock intervals. This study derives an analytical dynamic model of the difference between redundant CPU's due to differences in their clock intervals and uses this model with on-line parameter identification to idenitify the differences in the clock intervals. The ability of this methodology to accurately track errors due to asynchronisity generate an error signal with the effect of asynchronisity removed and this signal may be used to detect and isolate actual system failures.
Huynh, Loc C.↗
On the clock mechanism and the implausibility of the 35 day precessing disk in HZ Herculis/Hercules X-1
The concept of the precessing accretion disk in HZ Her/Her X-1 in its varied forms, to account for the 35 day periodicity in the X-ray flux, has met many objections from a number of workers on various grounds, but it is still being invoked in current publications. These objections are reviewed and additional arguments are presented against the precessing accretion disk model. The implausibility of the disk models is demonstrated. An alternate clock mechanism, based on nonlinear oscillations in the normal star, which provides the modulation of the mass flow is discussed.
Kondo, Y.↗
Modeling and Analysis of Asynchronous Systems Using SAL and Hybrid SAL
We present formal models and results of formal analysis of two different asynchronous systems. We first examine a mid-value select module that merges the signals coming from three different sensors that are each asynchronously sampling the same input signal. We then consider the phase locking protocol proposed by Daly, Hopkins, and McKenna. This protocol is designed to keep a set of non-faulty (asynchronous) clocks phase locked even in the presence of Byzantine-faulty clocks on the network. All models and verifications have been developed using the SAL model checking tools and the Hybrid SAL abstractor.
Tiwari, Ashish↗
A statistical model of the human core-temperature circadian rhythm
We formulate a statistical model of the human core-temperature circadian rhythm in which the circadian signal is modeled as a van der Pol oscillator, the thermoregulatory response is represented as a first-order autoregressive process, and the evoked effect of activity is modeled with a function specific for each circadian protocol. The new model directly links differential equation-based simulation models and harmonic regression analysis methods and permits statistical analysis of both static and dynamical properties of the circadian pacemaker from experimental data. We estimate the model parameters by using numerically efficient maximum likelihood algorithms and analyze human core-temperature data from forced desynchrony, free-run, and constant-routine protocols. By representing explicitly the dynamical effects of ambient light input to the human circadian pacemaker, the new model can estimate with high precision the correct intrinsic period of this oscillator ( approximately 24 h) from both free-run and forced desynchrony studies. Although the van der Pol model approximates well the dynamical features of the circadian pacemaker, the optimal dynamical model of the human biological clock may have a harmonic structure different from that of the van der Pol oscillator.
NASA Discipline Regulatory Physiology↗
Efficient parametric analysis of performance measures for communication networks
Efficient techniques for estimating performance measures in communication networks in a steady-state or transient setting are developed. These techniques may be used in a simulation environment or in connection with real-time observations. For Markov chain models, the recently proposed standard clock approach is extended, and a class of real-time algorithms for simultaneously generating multiple sample paths under different parameter sets is presented. Attention is focused on the link crash time estimation problem, where a 'crash' is defined as the first time a buffer overflows, given some initial conditions. An algorithm for estimating crash times under various traffic shocks is derived, where all estimates are obtained in parallel to an actual network's normal operation. An algorithm for crash time estimation of a G/D/1 link model is also derived using a different (perturbation-analysis-based) approach. Finally, extensive simulation results are provided to validate the proposed algorithms and compare them to brute-force simulation.
Cassandras, Christos G.↗
Verification of a Byzantine-Fault-Tolerant Self-stabilizing Protocol for Clock Synchronization
This paper presents the mechanical verification of a simplified model of a rapid Byzantine-fault-tolerant self-stabilizing protocol for distributed clock synchronization systems. This protocol does not rely on any assumptions about the initial state of the system except for the presence of sufficient good nodes, thus making the weakest possible assumptions and producing the strongest results. This protocol tolerates bursts of transient failures, and deterministically converges within a time bound that is a linear function of the self-stabilization period. A simplified model of the protocol is verified using the Symbolic Model Verifier (SMV). The system under study consists of 4 nodes, where at most one of the nodes is assumed to be Byzantine faulty. The model checking effort is focused on verifying correctness of the simplified model of the protocol in the presence of a permanent Byzantine fault as well as confirmation of claims of determinism and linear convergence with respect to the self-stabilization period. Although model checking results of the simplified model of the protocol confirm the theoretical predictions, these results do not necessarily confirm that the protocol solves the general case of this problem. Modeling challenges of the protocol and the system are addressed. A number of abstractions are utilized in order to reduce the state space.
Malekpour, Mahyar R.↗