Search NASA⌕ Search

SEARCH · Search NASA

Results for “computer architecture”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Charaterization of Emerging Computing Architectures for Dynamic Simulation of Future Power Grids with Large-Scale Power Electronics

The increasing penetration of power electronics in power grids significantly raises the computing requirements in a real-time (and/or fast) simulation of the power grid. The real-time simulation is an enabler for evaluating controllers, protection systems, new equipment, and twinning. In this paper, emerging computing architectures such as tensor processing units (TPU), neural/neuromorphic processing units (NPU), and quantum processing units (QPU) are introduced and characterized for the real-time (and/or fast) simulation of power electronics-dominated power grids. The metrics and the process to characterize emerging computing architectures to perform real-time (and/or fast) simulations of future power grids with power electronics are discussed. Three of the emerging computing units are characterized based on these metrics and the process developed. This characterization will enable identification and comparison of emerging computing architectures that can perform real-time (and/or fast) simulation of future power grids.

Choi, Jongchan↗
NASA NTRS1987

Computer architecture for efficient algorithmic executions in real-time systems: New technology for avionics systems and advanced space vehicles

Improvements and advances in the development of computer architecture now provide innovative technology for the recasting of traditional sequential solutions into high-performance, low-cost, parallel system to increase system performance. Research conducted in development of specialized computer architecture for the algorithmic execution of an avionics system, guidance and control problem in real time is described. A comprehensive treatment of both the hardware and software structures of a customized computer which performs real-time computation of guidance commands with updated estimates of target motion and time-to-go is presented. An optimal, real-time allocation algorithm was developed which maps the algorithmic tasks onto the processing elements. This allocation is based on the critical path analysis. The final stage is the design and development of the hardware structures suitable for the efficient execution of the allocated task graph. The processing element is designed for rapid execution of the allocated tasks. Fault tolerance is a key feature of the overall architecture. Parallel numerical integration techniques, tasks definitions, and allocation algorithms are discussed. The parallel implementation is analytically verified and the experimental results are presented. The design of the data-driven computer architecture, customized for the execution of the particular algorithm, is discussed.

Carroll, Chester C.↗
NASA NTRS1992

A computer architecture for intelligent machines

The theory of intelligent machines proposes a hierarchical organization for the functions of an autonomous robot based on the principle of increasing precision with decreasing intelligence. An analytic formulation of this theory using information-theoretic measures of uncertainty for each level of the intelligent machine has been developed. The authors present a computer architecture that implements the lower two levels of the intelligent machine. The architecture supports an event-driven programming paradigm that is independent of the underlying computer architecture and operating system. Execution-level controllers for motion and vision systems are briefly addressed, as well as the Petri net transducer software used to implement coordination-level functions. A case study illustrates how this computer architecture integrates real-time and higher-level control of manipulator and vision systems.

Lefebvre, D. R.↗
NASA NTRS1991

A computer architecture for intelligent machines

The Theory of Intelligent Machines proposes a hierarchical organization for the functions of an autonomous robot based on the Principle of Increasing Precision With Decreasing Intelligence. An analytic formulation of this theory using information-theoretic measures of uncertainty for each level of the intelligent machine has been developed in recent years. A computer architecture that implements the lower two levels of the intelligent machine is presented. The architecture supports an event-driven programming paradigm that is independent of the underlying computer architecture and operating system. Details of Execution Level controllers for motion and vision systems are addressed, as well as the Petri net transducer software used to implement Coordination Level functions. Extensions to UNIX and VxWorks operating systems which enable the development of a heterogeneous, distributed application are described. A case study illustrates how this computer architecture integrates real-time and higher-level control of manipulator and vision systems.

Lefebvre, D. R.↗
NASA NTRS1994

Advanced computer architecture specification for automated weld systems

This report describes the requirements for an advanced automated weld system and the associated computer architecture, and defines the overall system specification from a broad perspective. According to the requirements of welding procedures as they relate to an integrated multiaxis motion control and sensor architecture, the computer system requirements are developed based on a proven multiple-processor architecture with an expandable, distributed-memory, single global bus architecture, containing individual processors which are assigned to specific tasks that support sensor or control processes. The specified architecture is sufficiently flexible to integrate previously developed equipment, be upgradable and allow on-site modifications.

Katsinis, Constantine↗
DOE OSTI2022

Energy Use in Quantum Data Centers: Scaling the Impact of Computer Architecture, Qubit Performance, Size, and Thermal Parameters

As quantum computers increase in size, the total energy used by a quantum data center, including the cooling, will become a greater concern. The cooling requirements of quantum computers, which operate at temperatures near absolute zero, are determined by computing system parameters, including the number and type of physical qubits, the packaging efficiency of the system, and the split between circuits operating at cryogenic temperatures and those operating at room temperature. When combined with thermal system parameters such as cooling efficiency and cryostat heat transfer, the total energy use can be determined using a first-principles energy model. These models show that cooling of quantum computers differs in two fundamental ways from conventional data centers: (1) the energy required for cooling is much greater than the energy required for computation, and (2) the cooling loads are sensitive to the computational architecture. The temperature requirements for different qubit types can change energy requirements by orders of magnitude. Power use and computational power, as quantified by quantum volume, are analytically correlated. Approaches are identified for minimizing energy use in integrated quantum systems relative to computational power. Furthermore, designing a sustainable quantum computer will require both efficient cooling and system design that minimizes cooling requirements.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1987

A synchronized computational architecture for generalized bilateral control of robot arms

This paper describes a computational architecture for an interconnected high speed distributed computing system for generalized bilateral control of robot arms. The key method of the architecture is the use of fully synchronized, interrupt driven software. Since an objective of the development is to utilize the processing resources efficiently, the synchronization is done in the hardware level to reduce system software overhead. The architecture also achieves a balaced load on the communication channel. The paper also describes some architectural relations to trading or sharing manual and automatic control.

Bejczy, Antal K.↗
NASA NTRS1996

Computer Architecture. (Latest Citations from the Aerospace Database)

The bibliography contains citations concerning research and development in the field of computer architecture. Design of computer systems, microcomputer components, and digital networks are among the topics discussed. Multimicroprocessor system performance, software development, and aerospace avionics applications are also included. (Contains 50-250 citations and includes a subject term index and title list.)

BIBLIOGRAPHIES↗
NASA NTRS1977

Methodology of modeling and measuring computer architectures for plasma simulations

A brief introduction to plasma simulation using computers and the difficulties on currently available computers is given. Through the use of an analyzing and measuring methodology - SARA, the control flow and data flow of a particle simulation model REM2-1/2D are exemplified. After recursive refinements the total execution time may be greatly shortened and a fully parallel data flow can be obtained. From this data flow, a matched computer architecture or organization could be configured to achieve the computation bound of an application problem. A sequential type simulation model, an array/pipeline type simulation model, and a fully parallel simulation model of a code REM2-1/2D are proposed and analyzed. This methodology can be applied to other application problems which have implicitly parallel nature.

Wang, L. P. T.↗
NASA NTRS1987

Computing architecture for telerobots in earth orbit

Based on generic operational and computational requirements associated with the control of telerobots in earth orbit, a multibus-based distributed but integrated computing architecture is proposed. An experimental system of that kind under development at the Jet Propulsion Laboratory (JPL) is briefly described. It uses Intel Multibus I at both control station and remote robot (telerobot) computing nodes. An essential element within each multibus is a Unified (or Universal) Computer Control Subsystem (UCCS) for telerobot and control station motor components. The two multibus-based computing nodes can be linked by parallel or high speed serial links for real-time data transmission and for closing the real-time bilateral (force-reflecting) control loop between telerobot and control station. The experimental system is briefly commented, followed by a brief discussion of future development plans and possibilities.

Bejczy, A. K.↗
NASA NTRS2012

Real-Time Cognitive Computing Architecture for Data Fusion in a Dynamic Environment

A novel cognitive computing architecture is conceptualized for processing multiple channels of multi-modal sensory data streams simultaneously, and fusing the information in real time to generate intelligent reaction sequences. This unique architecture is capable of assimilating parallel data streams that could be analog, digital, synchronous/asynchronous, and could be programmed to act as a knowledge synthesizer and/or an "intelligent perception" processor. In this architecture, the bio-inspired models of visual pathway and olfactory receptor processing are combined as processing components, to achieve the composite function of "searching for a source of food while avoiding the predator." The architecture is particularly suited for scene analysis from visual data and odorant.

Duong, Tuan A.↗
NASA NTRS1989

Computational architecture for integrated controls and structures design

To facilitate the development of control structure interaction (CSI) design methodology, a computational architecture for interdisciplinary design of active structures is presented. The emphasis of the computational procedure is to exploit existing sparse matrix structural analysis techniques, in-core data transfer with control synthesis programs, and versatility in the optimization methodology to avoid unnecessary structural or control calculations. The architecture is designed such that all required structure, control and optimization analyses are performed within one program. Hence, the optimization strategy is not unduly constrained by cold starts of existing structural analysis and control synthesis packages.

Belvin, W. Keith↗
NASA NTRS1990

Multi-level Hierarchical Poly Tree computer architectures

Based on the concept of hierarchical substructuring, this paper develops an optimal multi-level Hierarchical Poly Tree (HPT) parallel computer architecture scheme which is applicable to the solution of finite element and difference simulations. Emphasis is given to minimizing computational effort, in-core/out-of-core memory requirements, and the data transfer between processors. In addition, a simplified communications network that reduces the number of I/O channels between processors is presented. HPT configurations that yield optimal superlinearities are also demonstrated. Moreover, to generalize the scope of applicability, special attention is given to developing: (1) multi-level reduction trees which provide an orderly/optimal procedure by which model densification/simplification can be achieved, as well as (2) methodologies enabling processor grading that yields architectures with varying types of multi-level granularity.

Padovan, Joe↗
DOE OSTI2019

Software for Sparse Tensor Decomposition on Emerging Computing Architectures

In this paper, we develop software for decomposing sparse tensors that is portable to and performant on a variety of multicore, manycore, and GPU computing architectures. The result is a single code whose performance matches optimized architecture-specific implementations. The key to a portable approach is to determine multiple levels of parallelism that can be mapped in different ways to different architectures, and we explain how to do this for the matricized tensor times Khatri--Rao product (MTTKRP), which is the key kernel in canonical polyadic tensor decomposition. Our implementation leverages the Kokkos framework, which enables a single code to achieve high performance across multiple architectures that differ in how they approach fine-grained parallelism. We also introduce a new construct for portable thread-local arrays, which we call compile-time polymorphic arrays. Not only are the specifics of our approaches and implementation interesting for tuning tensor computations, but they also provide a roadmap for developing other portable high-performance codes. As a last step in optimizing performance, we modify the MTTKRP algorithm itself to do a permuted traversal of tensor nonzeros to reduce atomic-write contention. Lastly, we test the performance of our implementation on 16- and 68-core Intel CPUs and the K80 and P100 NVIDIA GPUs, showing that we are competitive with state-of-the-art architecture-specific codes while having the advantage of being able to run on a variety of architectures.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2011

Heavy Lift Vehicle (HLV) Avionics Flight Computing Architecture Study

A NASA multi-Center study team was assembled from LaRC, MSFC, KSC, JSC and WFF to examine potential flight computing architectures for a Heavy Lift Vehicle (HLV) to better understand avionics drivers. The study examined Design Reference Missions (DRMs) and vehicle requirements that could impact the vehicles avionics. The study considered multiple self-checking and voting architectural variants and examined reliability, fault-tolerance, mass, power, and redundancy management impacts. Furthermore, a goal of the study was to develop the skills and tools needed to rapidly assess additional architectures should requirements or assumptions change.

Hodson, Robert F.↗
DOE OSTI2025

Building a quantum computing architecture using 3D superconducting cavities

Quantum computers promise advantages over classical machines for solving certain complex problems, but building processors that truly deliver this advantage remains a central challenge, particularly due to limited coherence times. Three-dimensional superconducting radio-frequency (SRF) cavities offer an attractive platform due to their exceptionally long lifetimes. However, since these harmonic systems require nonlinear elements, such as transmons, for control, additional losses are often introduced. In this talk, I will present a multimode quantum system based on an elliptical SRF cavity hosting two cavity modes weakly coupled to an ancillary transmon circuit. This architecture is carefully engineered to preserve coherence while enabling efficient control. By optimizing the design to mitigate transmon-induced decoherence, we realize single-photon lifetimes of 20.6 ms and 15.6 ms in the two modes, with pure dephasing times exceeding 40 ms. Using sideband interactions and error-resilient protocols, such as measurement-based correction and post-selection, we demonstrate high-fidelity state control, including preparation of Fock states up to N=20 with fidelities above 95% (to our knowledge, the highest reported to date), as well as high-fidelity two-mode entanglement. These results highlight 3D SRF cavities as a robust foundation for qudit-based quantum information processing, harnessing the large Hilbert space of cavity modes. I will conclude by outlining strategies to further enhance coherence in both cavities and ancilla qubits, and discuss pathways toward scaling this architecture into a larger quantum computing platform.

Roy, Tanay [Fermilab]↗
DOE OSTI2018

Performance Optimization of a Beam Dynamics PIC Code On Hybrid Computer Architectures

The self-consistent multi-particle tracking based on particle-in-cell method (PIC) has been widely used in particle accelerator beam dynamics study. However, the PIC simulation is time-consuming and needs to use modern parallel computers for high resolution applications. In this paper, we implemented and optimized a parallel beam dynamics PIC code on two types of hybrid parallel computer architectures: one is the GPU and GPU cluster, while the other is the "Knight Landing" CPU cluster.

Liu, Zhicong↗