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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Biological Information Signal Processor

Biological Information Signal Processor (BISP) is computing system analyzing data on deoxyribonucleic acid (DNA) sequences for molecular genetic analysis. Includes coprocessors, specialized microprocessors complementing present and future computers by performing rapidly most-time-consuming DNA-sequence-analyzing functions, establishing relationships (alignments) between both global sequences and defining patterns in multiple sequences. Also includes state-of-art software and data-base systems on both conventional and parallel computer systems to augment analytical abilities of developmental coprocessors.

Chow, Edward T.↗
DOE OSTI2021

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony↗
DOE OSTI2023

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony T.↗
DOE OSTI2026

The high level trigger and express data production at STAR

To meet the demands of the Beam Energy Scan phase-II (BES-II) program, the STAR experiment at the Relativistic Heavy Ion Collider (RHIC) developed a dual real-time framework consisting of a High Level Trigger (HLT) and an Express Data Production system (xProduction). The HLT operates online within the Data Acquisition (DAQ) chain on a dedicated multi-core CPU cluster with the option to offload compute-intensive kernels to Xeon Phi coprocessors. It uses parallelized algorithms, such as the Cellular Automaton (CA) Track Finder, to perform rapid tracking, vertexing, and event filtering. This allows it to select events of interest in real time and provide immediate feedback on detector and beam conditions. In contrast, the xProduction workflow runs concurrently and independently of the DAQ loop. It applies near offline-quality calibration and reconstruction within hours of data collection. The xProduction input is the express data stream, whose content can be enriched by HLT trigger/priority selections under DAQ/HLT resource constraints, and it uses the STAR calibration/conditions framework, incorporating online calibration/QA information when available. This enables early preliminary physics analysis, including the reconstruction of rare signals, such as hyperons and hypernuclei. It also provides collaboration-wide access to analysis-ready datasets. Together, the HLT and xProduction systems form a complementary architecture: the HLT performs online event selection while the xProduction chain delivers high-quality results within a short amount of time. This integrated framework has enabled the prompt reconstruction of the $^5_Λ$ He hypernucleus with high statistical significance and the efficient processing of hundreds of millions of heavy-ion collision events. In conclusion, its demonstrated scalability and robustness establish a model for future high-luminosity experiments requiring both online event filtering and rapid access to analysis-quality data.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2024

Probing Quantum Telecloning on Superconducting Quantum Processors

Quantum information cannot be perfectly cloned, but approximate copies of quantum information can be generated. Quantum telecloning combines approximate quantum cloning, more typically referred to as quantum cloning, and quantum teleportation. Quantum telecloning allows approximate copies of quantum information to be constructed by separate parties, using the classical results of a Bell measurement made on a prepared quantum telecloning state. Quantum telecloning can be implemented as a circuit on quantum computers using a classical coprocessor to compute classical feedforward instructions using if statements based on the results of a midcircuit Bell measurement in real time. We present universal symmetric optimal 1 → M telecloning circuits and experimentally demonstrate these quantum telecloning circuits for M = 2 up to M = 10, natively executed with real-time classical control systems on IBM Quantum superconducting processors, known as dynamic circuits. We perform the cloning procedure on many different message states across the Bloch sphere, on seven IBM Quantum processors, optionally using the error suppression technique X–X sequence digital dynamical decoupling. Two circuit optimizations are utilized: one that removes ancilla qubits for M = 2,3 , and one that reduces the total number of gates in the circuit but still uses ancilla qubits. Parallel single-qubit tomography with maximum likelihood estimation density matrix reconstruction is used in order to compute the mixed-state density matrices of the clone qubits, and clone quality is measured using quantum fidelity. These results present one of the largest and most comprehensive noisy intermediate-scale quantum computer experimental analyses on (single qubit) quantum telecloning to date. The clone fidelity sharply decreases to 0.5 for M > 5 , but for M = 2 , we are able to achieve a mean clone fidelity of up to 0.79 using dynamical decoupling.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

Introduction to Graphics Processing Units [Slides]

Graphics Processing Units are designed for fast graphics processing. Graphics are a form of arithemetic and have gradually evolved a design that is also usefule for non-graphics computing. They are not standalone, but work alongside a CPU(host)-coprocessor.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

CompF2: Theoretical Calculations and Simulation Topical Group Report

This report summarizes the work of the Computational Frontier topical group on theoretical calculations and simulation for Snowmass 2021. We discuss the challenges, potential solutions, and needs facing six diverse but related topical areas that span the subject of theoretical calculations and simulation in high energy physics (HEP): cosmic calculations, particle accelerator modeling, detector simulation, event generators, perturbative calculations, and lattice QCD (quantum chromodynamics). The challenges arise from the next generations of HEP experiments, which will include more complex instruments, provide larger data volumes, and perform more precise measurements. Calculations and simulations will need to keep up with these increased requirements. The other aspect of the challenge is the evolution of computing landscape away from general-purpose computing on CPUs and toward special-purpose accelerators and coprocessors such as GPUs and FPGAs. These newer devices can provide substantial improvements for certain categories of algorithms, at the expense of more specialized programming and memory and data access patterns.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Searching for Strongly Coupled Dark Sectors with Unsupervised and Generative Learning

Recipient of the URA Early Career Award for groundbreaking searches for dark matter arising from strongly coupled dark sectors with the CMS detector, pioneering work in ML-based model-independent anomaly detection for collider and astrophysics experiments, and leadership in the development of new AI/ML techniques to improve event reconstruction and detector simulation in particle physics, as well as novel strategies to accelerate AI inference and throughput with heterogeneous computing using coprocessors as a service.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1982

A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Yee, R.↗
NASA NTRS1984

A real-time, portable, microcomputer-based jet engine simulator

Modern piloted flight simulators require detailed models of many aircraft components, such as the airframe, propulsion system, flight deck controls and instrumentation, as well as motion drive and visual display systems. The amount of computing power necessary to implement these systems can exceed that offered by dedicated mainframe computers. One approach to this problem is through the use of distributed computing, where parts of the simulation are assigned to computing subsystems, such as microcomputers. One such subsystem, such as microcomputers. One such subsystem, a real-time, portable, microcomputer-based jet engine simulator, is described in this paper. The simulator will be used at the NASA Ames Vertical Motion Simulator facility to perform calculations previously done on the facility's mainframe computer. The mainframe will continue to do all other system calculations and will interface to the engine simulator through analog I/0. The engine simulator hardware includes a 16-bit microcomputer and floating-point coprocessor. There is an 8 channel analog input board and an 8 channel analog output board. A model of a small turboshaft engine/control is coded in floating-point FORTRAN. The FORTRAN code and a data monitoring program run under the control of an assembly language real-time executive. The monitoring program allows the user to isplay and/or modify simulator variables on-line through a data terminal. A dual disk drive system is used for mass storage of programs and data. The CP/M-86 operating system provides file management and overall system control. The frame time for the simulator is 30 milliseconds, which includes all analog I/0 operations.

Blech, R. A.↗
NASA NTRS1984

Floating-point function generation routines for 16-bit microcomputers

Several computer subroutines have been developed that interpolate three types of nonanalytic functions: univariate, bivariate, and map. The routines use data in floating-point form. However, because they are written for use on a 16-bit Intel 8086 system with an 8087 mathematical coprocessor, they execute as fast as routines using data in scaled integer form. Although all of the routines are written in assembly language, they have been implemented in a modular fashion so as to facilitate their use with high-level languages.

Mackin, M. A.↗
NASA NTRS1985

A SLAM II simulation model for analyzing space station mission processing requirements

Space station mission processing is modeled via the SLAM 2 simulation language on an IBM 4381 mainframe and an IBM PC microcomputer with 620K RAM, two double-sided disk drives and an 8087 coprocessor chip. Using a time phased mission (payload) schedule and parameters associated with the mission, orbiter (space shuttle) and ground facility databases, estimates for ground facility utilization are computed. Simulation output associated with the science and applications database is used to assess alternative mission schedules.

Linton, D. G.↗
NASA NTRS1985

Concurrent system-level error detection using a watchdog processor

This paper describes the design of a watchdog coprocessor for detecting hardware and software errors. The watchdog executes assertions about the process running on the main computer. Both general purpose an special purpose (used to check systems such as digital signal processors, telephone switching systems, or digital flight controllers) watchdog designs are described. The improvement of error coverage by adding control flow checking facilities is discussed. The implementation of the watchdog as a software process is presented.

Mahmood, A.↗
NASA NTRS1986

Hardware requirements: A new generation partial reflection radar for studies of the equatorial mesosphere

A new partial reflection (PR) radar is being developed for operation at the proposed Equatorial Observatory. The system is being designed to make maximum use of recent advances in solid-state technology in order to minimize the power requirements. In particular, it is planned to use a solid-state transmitter in place of the tube transmitters previously used in PR systems. Solid-state transmitters have the advantages that they do not need high voltage supplies, they do not require cathode heaters with a corresponding saving in power consumption and parts are readily available and inexpensive. It should be possible to achieve 15 kW peak powers with recently announced fast switching transistors. Since high mean powers are desirable for obtaining good signal-to-noise ratios, it is also planned to phase code the transmitted pulses and decode after coherent integration. All decoding and signal processing will be carried out in dedicated microprocessors before the signals are passed to a microcomputer for on-line analysis. Recent tests have shown that an Olivetti M24 micro (an IBM compatible) running an 8-MHz clock with a 8087 coprocessor can analyze data at least as fast as the minicomputers presently being used with the Adelaide PR rad ar and at a significantly lower cost. The processed winds data will be stored in nonvolatile CMOS RAM modules; about 0.5 to 1 Mbyte is required to store one week's information.

Vincent, R. A.↗
NASA NTRS1987

Communication and control in an integrated manufacturing system

Typically, components in a manufacturing system are all centrally controlled. Due to possible communication bottlenecking, unreliability, and inflexibility caused by using a centralized controller, a new concept of system integration called an Integrated Multi-Robot System (IMRS) was developed. The IMRS can be viewed as a distributed real time system. Some of the current research issues being examined to extend the framework of the IMRS to meet its performance goals are presented. These issues include the use of communication coprocessors to enhance performance, the distribution of tasks and the methods of providing fault tolerance in the IMRS. An application example of real time collision detection, as it relates to the IMRS concept, is also presented and discussed.

Shin, Kang G.↗
NASA NTRS1989

Conference on Real-Time Computer Applications in Nuclear, Particle and Plasma Physics, 6th, Williamsburg, VA, May 15-19, 1989, Proceedings

Papers on real-time computer applications in nuclear, particle, and plasma physics are presented, covering topics such as expert systems tactics in testing FASTBUS segment interconnect modules, trigger control in a high energy physcis experiment, the FASTBUS read-out system for the Aleph time projection chamber, a multiprocessor data acquisition systems, DAQ software architecture for Aleph, a VME multiprocessor system for plasma control at the JT-60 upgrade, and a multiasking, multisinked, multiprocessor data acquisition front end. Other topics include real-time data reduction using a microVAX processor, a transputer based coprocessor for VEDAS, simulation of a macropipelined multi-CPU event processor for use in FASTBUS, a distributed VME control system for the LISA superconducting Linac, a distributed system for laboratory process automation, and a distributed system for laboratory process automation. Additional topics include a structure macro assembler for the event handler, a data acquisition and control system for Thomson scattering on ATF, remote procedure execution software for distributed systems, and a PC-based graphic display real-time particle beam uniformity.

Pordes, Ruth↗
NASA NTRS1991

Program Computes Universal Transverse Mercator Projection

Computer program produces Gauss-Kruger (constant meridional scale) transverse Mercator projection, used to construct U.S. Army's universal transverse Mercator (UTM) grid system. Capable of mapping entire Northern Hemisphere of Earth (and, by symmetry of projection, entire Earth) accurately with respect to single principal meridian. Mathematically insensitive to proximity to pole or equator and insensitive to departure of meridian from central meridian. Useful to any mapmaking agency. FORTRAN 77 program developed on IBM PC-series computer equipped with Intel Math Coprocessor.

Wallis, David E.↗
NASA NTRS1992

Cascaded VLSI neural network architecture for on-line learning

High-speed, analog, fully-parallel, and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A computation intensive feature classification application was demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as an application specific coprocessor for solving real world problems at extremely high data rates.

Thakoor, Anilkumar P.↗