Results for “integrated circuit design” — Page 2

DOE OSTI2022

Quantum states of cylindrical surface charge density for modeling plasmonic circuit elements: Nanowires, nanorods, cavities, and waveguides

Nanostructures in the form of ellipsoids, prolate spheroids, rings, and cylinders are known to exhibit resonant surface and cavity modes with applications in nanophotonics and plasmonics and, more recently, in novel quantum experiments, in which control of plasmons and their interactions with plasmons, photons, phonons, excitons, and quantum emitters are desired. Nanorods and nanowires are examples of plasmonic structures with spectral properties of potential use as interconnects and circuit components. Additionally, estimates of the surface properties of these components are needed in circuit design and integrated systems. Here, we present a quantum Hamiltonian for the cylindrical surface charge density. We then study the photon excitation of plasmons on the cylindrical surface and calculate their scattering and radiative decay rate. Nonradiative decay of plasmons induces an efficient heating of the nanoparticle and can photoacoustically excite mechanical oscillations. Computational calculations are also presented for the plasmonic modes and the ensuing excitations of nanomechanical eigenmodes of nanoparticles with near-cylindrical symmetries.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗

DOE OSTI2026

IMPACT 2025-2026 Internship Poster

At Sandia National Laboratories, I developed a C++ program that converts printed circuit boards(PCB) and integrated circuits(IC) design files to be compatible for computed tomography (CT) simulations through Monte Carlo methods.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2020

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2022

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2022

Design and Challenges of Edge Computing ASICs on Front-End Electronics

In situ or hardware-embedded data processing of raw signals, close to their source, in radiation detectors is expected to provide dramatic improvements in data quality and volumes. However, the implementation of artificial neural networks (ANNs) in the front-end electronics, and the design of custom integrated circuits (ASICs), comes with challenges. In addition, detectors have to operate with limited power budget and implement complex functionalities in a very dense space. They often are exposed to extreme conditions as they work in high-radiation environments and/or cryogenic temperatures. This paper presents examples of applications and design methodologies for in-situ ANNs, along with the challenges of retaining the fidelity of the trained networks. For illustration, we use the problem of estimating the energy deposited by the radiation from digitized waveforms. The proposed implementation starts with an ML algorithm trained in Qkeras and eventually leads to an equivalent ASIC implementation. The associated design challenges in realizing energy and area efficient implementations in CMOS processes are reviewed. Novel approaches that employ hybrid technologies (combination of CMOS with memristors), in-memory computing models, and bio-inspired spiking neural networks are also highlighted

47 OTHER INSTRUMENTATION↗

DOE OSTI2021

Design and performance evaluation of a dual-circuit thermal energy storage module for air conditioners

We present experimental results and a validated numerical model of a dual-circuit phase-change thermal energy storage module for air conditioners. The module incorporates a phase-change material encapsulated in compressed expanded natural graphite foam. We used n-tetradecane as the PCM with a transition temperature (~4.5 °C) suitable for air-conditioning applications. Heat exchange to and from the module is accomplished through two fluid loops operating as a heat source and sink embedded inside multiple slabs of the composite material. This dual-circuit design enables easier integration with air-conditioning equipment and provides enhanced flexibility in system operation as compared to the state-of-the-art thermal storage systems. When integrated with an air-conditioner, this design will enable peak-load shaving and enhances operational efficiency. The thermal storage device was designed for a nominal storage capacity of ~ 3.5 kWh. We evaluated the heat transfer and energy storage performance of this device using standalone heat transfer experiments to estimate key thermal resistances and identify design improvements before integration with an air conditioner. The numerical model of the heat exchanger uses a combination of discretized and lumped parameter approaches to maintain a balance between accuracy and computational expense. Our analyses show that the geometric features and integration of fluid tubes are key contributors to the thermal contact resistance between the fluid and the thermal storage material, and consequently, to the overall performance of the thermal storage module. Our standalone experiments also identified important operating scenarios in which this thermal storage module can be used for air-conditioning in buildings.

25 ENERGY STORAGE↗

DOE OSTI2021

High-energy micrometre-scale pixel direct conversion X-ray detector

The objective of this work was to fabricate and characterize a new X-ray imaging detector with micrometre-scale pixel dimensions (7.8 µm) and high detection efficiency for hard X-ray energies above 20 keV. A key technology component consists of a monolithic hybrid detector built by direct deposition of an amorphous selenium film on a custom designed CMOS readout integrated circuit. Characterization was carried out at the synchrotron beamline 1-BM-B at the Advanced Photon Source of Argonne National Laboratory. The direct conversion detector demonstrated micrometre-scale spatial resolution with a 63 keV modulation transfer function of 10% at Nyquist frequency. In addition, spatial resolving power down to 8 µm was determined by imaging a transmission bar target at 21 keV. X-ray signal linearity, responsivity and lag were also characterized in the same energy range. Finally, phase contrast edge enhancement was observed in a phase object placed in the beam path. This amorphous selenium/CMOS detector technology can address gaps in commercially available X-ray detectors which limit their usefulness for existing synchrotron applications at energies greater than 50 keV; for example, phase contrast tomography and high-resolution imaging of nanoscale lattice distortions in bulk crystalline materials using Bragg coherent diffraction imaging. Here, the technology will also facilitate the creation of novel synchrotron imaging applications for X-ray energies at or above 20 keV.

36 MATERIALS SCIENCE↗

DOE OSTI2024

CryoPDK Development for 22nm FDSOI CryoCMOS

Cryogenic Process Design Kits (PDKs) are an indispensable tool in the design of complex integrated circuits across a wide spectrum of applications, from noble element detectors to Quantum Information Science, Superconducting Nanowire Single Photon Detectors (SNSPDs), and precision atomic clocks. The development of PDK-compatible SPICE models is a complex endeavor requiring test structures, measurements, model extraction and fitting. We will present the cryogenic modeling and development of a cryo-PDK for a 22nm FDSOI CMOS process for operation at 3.8 Kelvin.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2022

Design and Verification of An Open-Circuit Electro-Hydraulic Actuator System with An Integrated Electro-Hydraulic Unit

This paper proposes an electro-hydraulic actuator (EHA) system, and two novel-designed electro-hydraulic units (EHU) consisting of a fixed-displacement hydraulic pump and a variable-speed electric motor. Both the novel EHU designs integrate an electric machine and a hydraulic machine in a single unit, featuring compactness and power density. However, they differ for salient aspects such as power and electric machine cooling system. The EHA system features an open circuit design, where hydraulic hoses connect the EHU with a tank, a valve manifold, and the hydraulic cylinder. In this way, the proposed EHA technology can be used to implement distributed hydraulic actuation in a vehicle without requiring changes to the hydraulic actuators or at the overall layout of the hydraulic components with respect to the original vehicle design. A dedicated test rig is developed to verify the performance of the proposed EHA system. The efficiency of the EHA is measured in a steady state and under a realistic duty cycle of a commercial compact loader. The measured efficiency of the system can reach 54% with up to 20kN load and 6kW power level.

42 ENGINEERING↗

DOE OSTI2024

Modular Wide-bandgap String Inverters for Low-cost Medium-voltage Transformerless PV Systems

The proposed technology combines advances in wide-bandgap power electronics with breakthroughs in distributed and decentralized control to produce ultra-low-cost medium-voltage transformerless PV inverters that are composed of stackable lightweight blocks. Taken together, the proposed circuit designs and accompanying control strategies will yield integrated control+circuit (C2) blocks, each comprising a converter and local controller, that can be assembled in a modular fashion to obtain distributed conversion interfaces for next-generation commercial and utility-scale PV systems. We will utilize SiC devices to obtain C2 blocks that can individually operate at a voltage and power in excess of 1 kV and 100 kW, respectively, such that ensembles of series-connected blocks perform direct dc to three-phase ac conversion at medium voltages (e.g., 12 kV–35 kV) and at multi-MW power levels.

42 ENGINEERING↗

DOE OSTI2024

Toward an integrated multi-gigahertz ionizing particle diagnostic

Needs arising at both current and future accelerator facilities call for the development of radiation-hardened position-sensing diagnostics that can operate with multi-GHz repetition rates. Such instruments are likely to also have applications in the diagnosis of rapid plasma behavior. Here, building on the recent work of our Advanced Accelerator Diagnostics Collaboration, we are exploring the development of integrated multi-GHz ionizing particle detection systems based on chemical-vapor deposition diamond sensors, with the initial goal of producing a quadrant detector that can determine the intensity and centroid position of a particle beam at a repetition rate between 5 and 10 GHz. Results from our initial high-speed characterization work are presented, including those from a single-channel sensor with a GHz response. Approaches to achieving multi-GHz (5–10 GHz) rate capability, including the design of a dedicated Application Specific Integrated Circuit and the use of 3D RF-solver computer aided design software, are presented and discussed in more detail. 3D RF simulations suggest clean pulses of duration less than 250 ps (FWHM less than 125 ps) can be achieved with the approaches developed by this work.

43 PARTICLE ACCELERATORS↗

DOE OSTI2020

Xyce Case Study

With the elimination of underground nuclear testing and declining defense budgets, science-based stockpile stewardship requires increased reliance on high performance modeling and simulation of weapon systems. Today's weapon systems are comprised of various electrical components and systems. As a result, there is a need for tools that will allow the use of massively parallel modeling and simulation techniques on high performance computers in existing and future weapons' electrical systems models. The Xyce Parallel Electronic Simulator is a SPICE (Simulation Program with Integrated Circuit Emphasis)- compatible circuit simulator designed to run on large-scale parallel computing platforms, though it can also execute efficiently on a variety of architectures including single processor workstations. As a mature platform for large-scale parallel circuit simulation, Xyce supports standard capabilities available in commercial simulators, in addition to various devices and models specific to Sandia's needs. Specifically, Xyce aids in the design and verification of electrical and electronic circuits and systems prior to weapons' manufacturing and deployment.

45 MILITARY TECHNOLOGY, WEAPONRY, AND NATIONAL DEF↗

DOE OSTI2020

Xyce Case Study

With the elimination of underground nuclear testing and declining defense budgets, science-based stockpile stewardship requires increased reliance on high performance modeling and simulation of weapon systems. Today's weapon systems are comprised of various electrical components and systems. As a result, there is a need for tools that will allow the use of massively parallel modeling and simulation techniques on high performance computers in existing and future weapons' electrical systems models. The Xyce Parallel Electronic Simulator is a SPICE (Simulation Program with Integrated Circuit Emphasis)- compatible circuit simulator designed to run on large-scale parallel computing platforms, though it can also execute efficiently on a variety of architectures including single processor workstations. As a mature platform for large-scale parallel circuit simulation, Xyce supports standard capabilities available in commercial simulators, in addition to various devices and models specific to Sandia's needs. Specifically, Xyce aids in the design and verification of electrical and electronic circuits and systems prior to weapons' manufacturing and deployment.

45 MILITARY TECHNOLOGY, WEAPONRY, AND NATIONAL DEF↗

DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

FOS: Computer and information sciences↗