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Results for “integrated circuit reliability”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Nondestructive testing of microtab welds

Introduction of sinusoidal signal across welded structure to determine reliability of integrated circuit connections is discussed. In-phase frequencies and quadrature frequency functions are used to evaluate weld reliability. Schematic diagram of test equipment and components is provided.

Feinstein, L.↗
NASA NTRS2005

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

CMOS integrated circuits↗
NASA NTRS2004

Self-Recovery Experiments in Extreme Environments Using a Field Programmable Transistor Array

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. However, current technology can only ensure very limited lifetime in extreme environments. This paper describes novel experiments that allow adaptive in-situ circuit redesign/reconfiguration during operation in extreme temperature and radiation environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip (FPTA-2), which recovers functionality for temperatures until 28 C and with total radiation dose up to 250kRad.

space vehicle electronics↗
NASA NTRS1967

Method of improving contact bonds in silicon integrated circuits

Fabrication method produces stable and reliable metallic systems for interconnections, contact pads, and bonded leads in silicon planar integrated circuits. The method is based on substrate isolation of the interconnection metal from the contact pad and bonded wire.

Lytle, W. J.↗
NASA NTRS1985

Study of Contact Resistances in Integrated Circuits

Techniques explored in search for rapid, reliable test. Resistances of aluminum/silicon contacts and methods to measure subjects of NASA report. Study with three tasks undertaken to evaluate nature and reliability of large numbers of semiconductor contacts of type now being fabricated in integrated circuits: Develop yield analysis for series strings of contacts using wafer-level electrical measurements, and identify different types of faults by visual inspection; develop wafer-level tests to evaluate reliability of contact strings; and develop mathematical model for current flow in contacts and examine contact region for evidence of micro-alloying.

Buehler, M. G.↗
NASA NTRS1991

Design and status of the RF-digitizer integrated circuit

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Rayhrer, B.↗
NASA NTRS1971

Television multiplexing system

System with single, standard, wideband line transmits ten or more real time TV video data displays over hard wire to recorders more than 22.5 km from source. Digital logic and integrated circuits ensure high reliability and low maintenance. System is adaptable for video sampling applications.

Simpkins, L. G.↗
NASA NTRS2015

The NASA Electronic Parts and Packaging (NEPP) Program: Overview and the New Tenets for Cost Conscious Mission Assurance on Electrical, Electronic, and Electromechanical (EEE) Parts

The NEPP Program focuses on the reliability aspects of electronic devices (integrated circuits such as a processor in a computer). There are three principal aspects of this reliability: 1) Lifetime, inherent failure and design issues related to the EEE parts technology and packaging; 2) Effects of space radiation and the space environment on these technologies, and; 3) Creation and maintenance of the assurance support infrastructure required for mission success. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment, and to ensure that appropriate EEE parts research is performed to meet NASA mission assurance needs. NEPPs FY15 goals are to represent the NASA voice to the greater aerospace EEE parts community including supporting anti-counterfeit and trust, provide relevant guidance to cost-effective missions, aid insertion of advanced (and commercial) technologies, resolve unexpected parts issues, ensure access to appropriate radiation test facilities, and collaborate as widely as possible with external entities. In accordance with the changing mission profiles throughout NASA, the NEPP Program has developed a balanced portfolio of efforts to provide agency-wide assurance for not only traditional spacecraft developments, but also those in-line with the new philosophies emerging worldwide. In this presentation, we shall present an overview of this program and considerations for EEE parts assurance as applied to cost conscious missions.

space radiation↗
NASA NTRS1996

Waveguide Transfer Switch Driver Multichip Module

This paper summarizes and reports a radiation hardened Spacecraft Integrated Circuit Technology to be flown on board the Cassini spacecraft in 1997 A.D. The Multichip Module has been designed to have an operating life of fifeteen (15) years with appropriate derating guidelines for high reliability.

integrated circuits Cassini multichip module space↗
NASA NTRS1985

Wire-Identification Instrument

Instrument automatically tests each wire in multiwire cable and identifies specified wire to be segregated or labeled and locates wire connected to specified connector pin. Instrument made with readily available CMOS integrated circuits. More efficient and reliable than conventional continuity testers and less expensive than computer controlled units.

Lonborg, J. O.↗
NASA NTRS2005

Design for ASIC reliability for low-temperature applications

In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.

reliability↗