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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Advanced flight computer. Special study

This report documents a special study to define a 32-bit radiation hardened, SEU tolerant flight computer architecture, and to investigate current or near-term technologies and development efforts that contribute to the Advanced Flight Computer (AFC) design and development. An AFC processing node architecture is defined. Each node may consist of a multi-chip processor as needed. The modular, building block approach uses VLSI technology and packaging methods that demonstrate a feasible AFC module in 1998 that meets that AFC goals. The defined architecture and approach demonstrate a clear low-risk, low-cost path to the 1998 production goal, with intermediate prototypes in 1996.

Coo, Dennis↗
NASA NTRS1996

Development of the SEASIS instrument for SEDSAT

Two SEASIS experiment objectives are key: take images that allow three axis attitude determination and take multi-spectral images of the earth. During the tether mission it is also desirable to capture images for the recoiling tether from the endmass perspective (which has never been observed). SEASIS must store all its imagery taken during the tether mission until the earth downlink can be established. SEASIS determines attitude with a panoramic camera and performs earth observation with a telephoto lens camera. Camera video is digitized, compressed, and stored in solid state memory. These objectives are addressed through the following architectural choices: (1) A camera system using a Panoramic Annular Lens (PAL). This lens has a 360 deg. azimuthal field of view by a +45 degree vertical field measured from a plan normal to the lens boresight axis. It has been shown in Mr. Mark Steadham's UAH M.S. thesis that his camera can determine three axis attitude anytime the earth and one other recognizable celestial object (for example, the sun) is in the field of view. This will be essentially all the time during tether deployment. (2) A second camera system using telephoto lens and filter wheel. The camera is a black and white standard video camera. The filters are chosen to cover the visible spectral bands of remote sensing interest. (3) A processor and mass memory arrangement linked to the cameras. Video signals from the cameras are digitized, compressed in the processor, and stored in a large static RAM bank. The processor is a multi-chip module consisting of a T800 Transputer and three Zoran floating point Digital Signal Processors. This processor module was supplied under ARPA contract by the Space Computer Corporation to demonstrate its use in space.

Maier, Mark W.↗
NASA NTRS1996

Development of the command data system and ground software for the SEDSAT-1 microsatellite

SEDSAT-1 is designed to be a low cost scientific satellite which is to be used to perform a minimum of five tasks which include: (1) the acquisition of a number of important parameters associated with the tethering processes from the payloads perspective (such as accelerations incurred and imaging data of the tether during deployment), (2) to act as a remote sensing platform for making measurements of the Earth's Atmosphere (allowing research to be performed in such areas as vertical lightning observation, visible light spectrography, and cloud cover studies, (3) to act as a general purpose amateur radio communication satellite relaying information back to earth, (4) to demonstrate the feasibility of the deployment in low earth orbit of advanced technology such as the Gallium Arsenide Solar Cells, Nickel Metal Hydride batteries, and multi-chip module technology and, (5) to support student's active participation in applying the disciplines of engineering and science to space-based hardware platforms. The project includes the Three-axis Accelerometer System, TAS, Experiment which is designed to report the accelerations that the satellite undergoes during the tethering operations and during the second phase of the mission when the free floating satellite comes in contact with orbit debris. The SEASIS (SEDS Earth, Atmosphere, and Space Imaging System) is another SEDSAT experiment designed to provide images of the tether during its deployment and the earth during the second phase of the mission. To control these experiments and virtually all other satellite operations the Command Data System, CDS is employed. This system utilizes a moderate complexity micro-controller controlled by tasks operating under a real-time operating system to dynamically monitor and control the satellite. The scope of this researchers efforts has been in the general area of coordinating and assisting the student researchers with the development of the CDS and ground station interfaces. This included the low level CDS hardware design and the formulization of a general software plan and schedule for both the CDS and ground station portions of the project.

Wells, B. Earl↗
NASA NTRS1995

Low volume packaging for a microinstrumentation system

A folding, multi-platform assembly has been developed for the packaging of a multi-chip microinstrumentation system. The assembly includes three solid platforms connected by flexible micromachined ribbon cables and it can be populated by sensors and electronics from a variety of technologies including surface mount and integrated circuit (IC) processes. The entire structure is fabricated from a four-inch silicon wafer using a simple four mask process and a post-process EDP etch. The micromachined ribbon cables allow the platform assembly to be folded into a three level structure with control electronics on the bottom level, microsensors and interface electronics on the second level, and sensors that need environmental access on the top level. Using the silicon multi-platform assembly, a prototype microinstrumentation system has been developed that includes a microcontroller unit and sensors for measuring temperature, barometric pressure, humidity, altitude, and acceleration as well as a telemetry device for wireless communication. When folded in the three level structure, this microsystem occupies only 5 cc and can be placed in an outer case the size of a wristwatch.

Mason, A.↗
NASA NTRS1995

Advanced packaging for Integrated Micro-Instruments

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

Lyke, James L.↗
NASA NTRS1997

A Novel Silicon Micromachined Integrated MCM Thermal Management System

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high heat flux applications, respectively. The high heat load application of particular interest in mind is the motor controller developed by Martin Marietta for Nasa to control the thruster's directional actuators on space vechicles. Work is also proposed to develop highly advanced and improved porous wick structures for use in advanced heat loops. The porous wick will be micromachined from silicon using MEMS technology, thus permitting far superior control of pore size and pore distribution (over wicks made from sintered n-ietals), which in turn is expected to led to significantly improved heat loop performance.

Kazmierczak, M. J.↗
NASA NTRS1996

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Le, Binh Q.↗
NASA NTRS1998

Seal the Deal

AvanTeco Corporation has developed a moisture/contaminant sensor chip. This newly developed chip rapidly responds to the presence of moisture, especially in condensed form and in presence of ionic impurities. It determines whether moisture has permeated a hermetically sealed package or a plastic encapsulated microcircuit. The sensor chip was designed as a "go/no go" chip, which is assembled with other chips in a multi-chip module to assess the risk of failure for the entire module. It has been commercialized and is sold by Revtek, Inc.

Source record↗
NASA NTRS2003

The Neptune/Triton Explorer Mission: A Concept Feasibility Study

Technological advances over the next 10 to 15 years promise to enable a number of smaller, more capable science missions to the outer planets. With the inception of miniaturized spacecraft for a wide range of applications, both in large clusters around Earth, and for deep space missions, NASA is currently in the process of redefining the way science is being gathered. Technologies such as 3-Dimensional Multi-Chip Modules, Micro-machined Electromechanical Devices, Multi Functional Structures, miniaturized transponders, miniaturized propulsion systems, variable emissivity thermal coatings, and artificial intelligence systems are currently in research and development, and are scheduled to fly (or have flown) in a number of missions. This study will leverage on these and other technologies in the design of a lightweight Neptune orbiter unlike any other that has been proposed to date. The Neptune/Triton Explorer (NExTEP) spacecraft uses solar electric earth gravity assist and aero capture maneuvers to achieve its intended target orbit. Either a Taurus or Delta-class launch vehicle may be used to accomplish the mission.

Esper, Jaime↗
NASA NTRS2004

Tunable All-Solid-State Local Oscillators to 1900 GHz

We present a status report of an ongoing effort to develop robust tunable all-solid-state sources up to 1900 GHz for the Heterodyne Instrument for the Far Infrared (HIFI) on the Herschel Space Observatory. GaAs based multi-chip power amplifier modules at W-band are used to drive cascaded chains of multipliers. We have demonstrated performance from chains comprised of four doublers up to 1600 GHz as well as from a x2x3x3 chain to 1900 GHz. Measured peak output power of 23 (micro)W at 1782 GHz and 2.6 (micro)W at 1900 GHz has been achieved when the multipliers are cooled to 120K. The 1900 GHz tripler was pumped with a four anode tripler that produces a peak of 4 mW at 630 GHz when cooled to 120 K. We believe that these sources can now be used to pump hot electron bolometer (HEB) heterodyne mixers.ter (HEB) heterodyne mixers.

local oscillator↗
NASA NTRS2007

MCM Polarimetric Radiometers for Planar Arrays

A polarimetric radiometer that operates at a frequency of 40 GHz has been designed and built as a prototype of multiple identical units that could be arranged in a planar array for scientific measurements. Such an array is planned for use in studying the cosmic microwave background (CMB). All of the subsystems and components of this polarimetric radiometer are integrated into a single multi-chip module (MCM) of substantially planar geometry. In comparison with traditional designs of polarimetric radiometers, the MCM design is expected to greatly reduce the cost per unit in an array of many such units. The design of the unit is dictated partly by a requirement, in the planned CMB application, to measure the Stokes parameters I, Q, and U of the CMB radiation with high sensitivity. (A complete definition of the Stokes parameters would exceed the scope of this article. In necessarily oversimplified terms, I is a measure of total intensity of radiation, while Q and U are measures of the relationships between the horizontally and vertically polarized components of radiation.) Because the sensitivity of a single polarimeter cannot be increased significantly, the only way to satisfy the high-sensitivity requirement is to make a large array of polarimeters that operate in parallel. The MCM includes contact pins that can be plugged into receptacles on a standard printed-circuit board (PCB). All of the required microwave functionality is implemented within the MCM; any required supporting non-microwave ("back-end") electronic functionality, including the provision of DC bias and control signals, can be implemented by standard PCB techniques. On the way from a microwave antenna to the MCM, the incoming microwave signal passes through an orthomode transducer (OMT), which splits the radiation into an h + i(nu) beam and an h - i(nu) beam (where, using complex-number notation, h denotes the horizontal component, nu denotes the vertical component, and +/-i denotes a +/-90deg phase shift). Each of these beams enters the MCM through one of two WR-22 waveguide input terminals in the lid of the MCM. The h + i(nu0 and h - i(nu) signals are amplified, then fed to a phase-discriminator hybrid designed specifically to fit the predominantly planar character of the MCM geometry and to enable determination of Q and U. The phase-discriminator hybrid generates four outputs, which are detected and used to calculate I, Q, and U.

Kangaslahti, Pekka↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗
NASA NTRS2003

SpaceWire Driver Software for Special DSPs

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Clark, Douglas↗
DOE OSTI2025

Packaging a 650V/400A GaN Half-bridge Power Module with Ultra-low Parasitics for Electric Vehicle Drive Applications

This paper proposes a compact and efficient half-bridge power module with three 650 V / 150 A GaN dies in parallel. The power module incorporates a main power printed circuit board (PCB), an interface PCB, and a flex PCB to achieve low parasitics in both power loop and gate-side connection, resolving the issue of high parasitics typically encountered with wire bonding in high-current applications. Additionally, the interface PCB decouples the design constraints between the power loop and the gate loops. The proposed design is optimized with a vertical loop configuration to reduce power loop inductance through magnetic flux cancellation. Finite element analysis indicates that the power loop inductance is 0.58 nH at 100 MHz, while the maximum die junction temperature reaches 131 °C under an ambient temperature of 65 °C and a load current of 385 A. The proposed multi-piece PCB structure reduces the inductance of the drive circuit to minimize EMI and to mitigate false triggering. At the same time, it reduces impedance mismatches across different driver circuits, thereby achieving dynamic current sharing in multi-chip parallel configurations. Under simulation conditions of 400 V / 385 A, the current imbalance among chips was limited to 5 A. A 400 V / 385 A double-pulse test was conducted to experimentally validate the performance of the proposed power module.

30 DIRECT ENERGY CONVERSION↗
NASA NTRS1998

64Mb COTS DRAMs: A Variety of SEE Responses

Advanced commercial DRAMs are particularly attractive to designers for space applications needing large memory arrays due to resulting savings in mass, volume, and power.

(MCMs)↗