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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Precision Cleaning Verification of Nonvolatile Residues by Using Water, Ultrasonics, and Turbidity Analyses

Chlorofluorocarbons (CFC's) in the atmosphere are believed to present a major environmental problem because they are able to interact with and deplete the ozone layer. NASA has been mandated to replace chlorinated solvents in precision cleaning, cleanliness verification, and degreasing of aerospace fluid systems hardware and ground support equipment. KSC has a CFC phase-out plan which provides for the elimination of over 90 percent of the CFC and halon use by 1995. The Materials Science Laboratory and KSC is evaluating four analytical methods for the determination of nonvolatile residues removal by water: (1) infrared analyses using an attenuated total reflectance; (2) surface tension analyses, (3) total organic content analyses, and (4) turbidity analyses. This research project examined the ultrasonic-turbidity responses for 22 hydrocarbons in an effect to determine: (1) if ultrasonics in heated water (70 C) will clean hydrocarbons (oils, greases, gels, and fluids) from aerospace hardware; (2) if the cleaning process by ultrasonics will simultaneously emulsify the removed hydrocarbons in the water; and (3) if a turbidimeter can be used successfully as an analytical instrument for quantifying the removal of hydrocarbons. Sixteen of the 22 hydrocarbons tested showed that ultrasonics would remove it at least 90 percent of the contaminated hydrocarbon from the hardware in 10 minutes or less giving a good ultrasonic-turbidity response. Six hydrocarbons had a lower percentage removal, a slower removal rate, and a marginal ultrasonic-turbidity response.

Skinner, S. Ballou↗
NASA NTRS1993

Nonvolatile Array Of Synapses For Neural Network

Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.

Tawel, Raoul↗
NASA NTRS1994

Nonvolatile GaAs Random-Access Memory

Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

Katti, Romney R.↗
NASA NTRS1995

A Real-Time Nonvolatile Residue (NVR) Monitor

New development and application of device described in "Surface-Acoustic-Wave Piezoelectric Microbalance," (LAR-14476). Active sensing element of Real-Time NVR Monitor comprises pair of piezoelectric surface-acoustic-wave resonators resonating at frequency of 200 MHz. Bare, uncoated resonator exposed to atmosphere and directly in contact with airborne volatile and nonvolatile materials leaving residues on surface. Resonant frequency of exposed resonator decreases with increasing mass of adsorbed residue; resulting beat frequency between two resonators increases with mass and serves as sensitive real-time indication of airborne contaminants or non-volatile residue.

Bowers, William D.↗
NASA NTRS1996

Performance Enhancement of a High Speed Jet Impingement System for Nonvolatile Residue Removal

A high speed jet impingement cleaning facility has been developed to study the effectiveness of the nonvolatile residue removal. The facility includes a high pressure air compressor which charges the k-bottles to supply high pressure air, an air heating section to vary the temperature of the high pressure air, an air-water mixing chamber to meter the water flow and generate small size droplets, and a converging- diverging nozzle to deliver the supersonic air-droplet mixture flow to the cleaning surface. To reliably quantify the cleanliness of the surface, a simple procedure for measurement and calibration is developed to relate the amount of the residue on the surface to the relative change in the reflectivity between a clean surface and the greased surface. This calibration procedure is economical, simple, reliable, and robust. a theoretical framework is developed to provide qualitative guidance for the design of the test and interpretation of the experimental results. The result documented in this report support the theoretical considerations.

Klausner, James F.↗
NASA NTRS2001

Nonvolatile Memory Solution for Near-Term NASA Missions

Nonvolatile memory (NVM) system that could reliably function in extreme environments is one of the most critical components for many spacecrafts being developed for NASA missions to be launched in next four to seven years. NVM supports the computer system in saving and updating critical state data required for a warm restart after power cycling or in case of a power bus failure. It also provides a power independent mass storage capacity for the scientific data gathered by the instruments. In some cases the window for gathering such data is very small and occurs only once in a given mission. Commercially popular and fully developed Flash NVM technology is inappropriate for many reasons such as the limited read write cycles with slower access speeds, radiation intolerance, higher Single Event Upsets (SEU) rates, etc. It is desirable to have an NVM system based upon a robust cell technology making it immune to the SEUs and with sufficient radiation hardness. Availability of such NVM system seems to be still 5 to 10 years in the future. Meanwhile, it is possible to provide an interim hybrid solution by combining the existing rad-hard technologies. Additional information is contained in the original extended abstract.

Patel, J. U.↗
NASA NTRS2000

Mechanisms of Protonic Nonvolatile Memory Device

A nonvolatile memory device based on protonic transport in oxides has been proposed. The mobile H+ ions are introduced into the SiO2 layer by annealing Si/SiO2/Si structures in H2 at temperatures greater than 500 deg C. This effect has only been observed for confined oxides that have been annealed at greater than or equal to 1100 C prior to the hydrogenation anneal. This includes buried oxides such as Unibond and SIMOX as well as thermal oxides annealed with a polysilicon cap. An applied field moves the charge within the oxide and the charge stops moving when the field is removed. In a memory device, the hydrogen-annealed oxide is the gate oxide and the position of the mobile charge is sensed by the shift of the I-V curve. Much is still not understood about the motion of the charge across the buried oxide. Previous work has assumed that H+ transport and the time it takes to traverse the oxide is governed by interactions within the bulk of the oxide. Based on parameters that affect the transport time, we conclude that H+ trapping and detrapping at the Si/SiO2 interface are more important than H+ interactions within the oxide bulk. These parameters include the applied field, the H+ concentration and the oxide thickness. One consequence is that projections of device write-time based on the previous assumptions of H+ transport mechanisms may be overly optimistic.

P J Macfarlane↗
NASA NTRS2004

Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

Oldham, Timothy R.↗
NASA NTRS2007

Nonvolatile Analog Memory

A nonvolatile analog memory uses pairs of ferroelectric field effect transistors (FFETs). Each pair is defined by a first FFET and a second FFET. When an analog value is to be stored in one of the pairs, the first FFET has a saturation voltage applied thereto, and the second FFET has a storage voltage applied thereto that is indicative of the analog value. The saturation and storage voltages decay over time in accordance with a known decay function that is used to recover the original analog value when the pair of FFETs is read.

MacLeod, Todd C.↗
NASA NTRS1994

Nonvolatile random access memory

A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

Wu, Jiin-Chuan↗
NASA NTRS2010

Nonvolatile Memory Technology for Space Applications

This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

Oldham, Timothy R.↗
NASA NTRS2010

SONOS Nonvolatile Memory Cell Programming Characteristics

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

MacLeod, Todd C.↗
NASA NTRS2011

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

Mitchell, Cody↗
NASA NTRS2012

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Irom, Farokh↗