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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

Rao, Vikram↗
NASA NTRS2011

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

Mitchell, Cody↗
DOE OSTI2024

Local structure effects of carbon-doping on the phase change material Ge 2 Sb 2 Te 5

Ge 2 Sb 2 Te 5 is used in phase change memory, a nonvolatile memory technology, due to its phase change properties. The primary advantage of phase change memory over the state-of-the-art (flash memory) is its simple and small device geometry, which allows for denser nodes and lower power consumption. In phase change memory, resistive heating induces fast switching between the high resistance amorphous and low resistance crystalline phases, corresponding to storage of low and high digital states, respectively. However, the instability of the amorphous phase of Ge 2 Sb 2 Te 5 presents issues with processing and long-term data storage; such issues can be resolved by C doping, which stabilizes the amorphous phase and raises the crystallization temperature. To better understand the local structural effects of C doping on Ge 2 Sb 2 Te 5 , in situ Ge K-edge X-ray absorption spectroscopy measurements were taken during heating of films with various C doping concentrations. Here, the range of structural transformation temperatures derived from X-ray absorption near-edge structure analysis across the C doping series proved narrower than crystallization temperatures reported in similar in situ X-ray diffraction experiments, which may reflect changes in local structure that precede long-range ordering during crystallization. In addition, rigorous extended X-ray absorption fine structure fitting across and between temperature series revealed effects of C doping on the rigidity of Ge–Te bonds at low (2 at% and 4 at%) C concentrations.

Langhout, John D.↗
DOE OSTI2025

Harnessing ferro-valleytricity in pentalayer rhombohedral graphene for memory and compute

Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. In conclusion, our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.

2D materials↗
DOE OSTI2025

A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture

The flourishing development of neural networks that require exponentially growing amounts of data has presented an elevated demand for memory footprint. To address this, researchers have been exploring hardware accelerators with innovative memory architectures like 3D memory. These 3D memory architectures offer enhanced storage capacity and processing capabilities, at a cost of rising on-chip temperature during operation. Hafnium Zirconium Oxide (HZO) based Ferroelectric Random Access Memory (FeRAM) is a promising nonvolatile memory candidate in neural network hardware accelerators for its outstanding write performance and reliability. However, its implementation in the architecture regarding the temperature-dependent ferroelectric switching behavior has not been well studied. In this work, we study the thermal impacts on polarization switching through experimental devices and simulation results. We conduct the circuit and architecture-level simulations to showcase that one can exploit this temperature rise to reduce FeRAM's write voltage and write energy due to its unique temperature-activated polarization switching mechanisms. As the on-chip temperature increases to 351K (ambient temperature at 300K) due to neural network workloads, the access energy per bit can be reduced by 27.6% when a dynamic write voltage is applied.

36 MATERIALS SCIENCE↗
NASA NTRS1975

Investigation of field induced trapping on floating gates

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Gosney, W. M.↗
NASA NTRS1992

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

Thin film ferroelectric capacitors comprising a ferroelectric film sandwiched between electrodes for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode. The anneal is done so as to form the interface between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550 to 600 C for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the nonswitching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the nonswitching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Thakoor, Sarita↗
DOE OSTI2025

Effect of Gamma Radiation on TaOₓ ECRAM

Electrochemical random access memory (ECRAM) is an emerging three-terminal nonvolatile memory (NVM) with highly controllable channel conductance which is promising for use as an analog memory (or synapse) in analog in-memory computing (IMC) systems. Energy-efficient analog IMC computing is particularly desirable for power-constrained, high-radiation environments such as satellites. However, little is known about the suitability of ECRAM for use in a total ionizing dose (TID) environment. Here, this work investigates the effect of Co-60 gamma radiation on the channel conductance and noise—two properties critical for analog IMC systems—of a TaO x -based ECRAM up to 17.3 Mrad(SiO 2 ) for both low- and high-channel-conductance state devices. A transient increase in conductance is observed in response to radiation which consists of two elements: an immediate increase in conductivity due to photocurrent and a secondary increase in conductivity, which has a slower rise and saturation and can persist for hours after exposure. This secondary, persistent photoconductivity is attributed to charging caused by hole trapping. These transient effects would not likely occur in a space environment due to the low dose rate compared with this experiment. No permanent change is found in the low conductance state (LCS) following exposure and the minor shift in the high conductance change would be less significant than the regular retention decay in this state. A permanent increase in the random telegraph noise is observed, possibly due to increased traps created in the channel. This work demonstrates that TaO x -based ECRAM is suitable for use in spaceborne analog IMC systems that are subject to significant TID.

ECRAM↗
NASA NTRS1994

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

Thin film ferroelectric capacitors (10) comprising a ferroelectric film (18) sandwiched between electrodes (16 and 20) for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode (20). The anneal is done so as to form the interface (22) between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550.degree. to 600.degree. C. for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the non-switching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the non-switching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Thakoor, Sarita↗
DOE OSTI2024

Ultrafast high-endurance memory based on sliding ferroelectrics

The persistence of voltage-switchable collective electronic phenomena down to the atomic scale has extensive implications for area- and energy-efficient electronics, especially in emerging nonvolatile memory technology. We investigate the performance of a ferroelectric field-effect transistor (FeFET) based on sliding ferroelectricity in bilayer boron nitride at room temperature. Sliding ferroelectricity represents a different form of atomically thin two-dimensional (2D) ferroelectrics, characterized by the switching of out-of-plane polarization through interlayer sliding motion. We examined the FeFET device employing monolayer graphene as the channel layer, which demonstrated ultrafast switching speeds on the nanosecond scale and high endurance exceeding 10 11 switching cycles, comparable to state-of-the-art FeFET devices. These characteristics highlight the potential of 2D sliding ferroelectrics for inspiring next-generation nonvolatile memory technology.

Science & Technology - Other Topics↗
DOE OSTI2025

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗
NASA NTRS1977

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Gosney, W. M.↗
NASA NTRS1971

Nonvolatile read/write memory element - A concept

Memory, with limited number of programming cycles, is achieved by using verticle, fusible links in series with oxide breakthrough elements. Memory elements are fabricated with integrated circuit technology and are ideal for low power digital computer application.

Cricchi, J. R.↗
NASA NTRS1971

Nonvolatile read/write memory element - A concept

Bidirectional MOS driver, integrated with diode matrix reduces fuse read current to only that of junction leakage and transient MOS gate charging current. No current, except junction leakage current, flows in unaddressed cells. Current required to drive MOS gate flows through unfused branch only during read mode.

Cricchi, J. R.↗
NASA NTRS2010

Electrically Variable Resistive Memory Devices

Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

Liu, Shangqing↗
NASA NTRS1994

Solid State Memory Study Final Report

Existing and future solid state nonvolatile memory technologies are described and evaluated in this report. Solid state memory technologies can offer size, speed, power, weight, and ruggedness advantages over conventional moving media storage technologoies such as disk or tape. This technology list is a broad sampling of past, present, emerging, and future solid state memory technologies.

Solid State Memory↗