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At least 37 records · Page 2

Robust Bioinformatics Recognition with VLSI Biochip Microsystem

A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

bioinformatics↗

Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. We are developing a radiation hard readout integrated circuit (ROIC) in 28nm CMOS with on-chip machine learning (ML) for future intelligent pixel detectors. We will show track parameter predictions using a neural network within a single layer of silicon and hardware tests on the first tape-outs produced with TSMC. Preliminary results indicate that reading out featurized clusters from particles above a modest momentum threshold could enable using pixel information at 40 MHz.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Implementing direct, spatially isolated problems on transputer networks

Parametric studies were performed on transputer networks of up to 40 processors to determine how to implement and maximize the performance of the solution of problems where no processor-to-processor data transfer is required for the problem solution (spatially isolated). Two types of problems are investigated a computationally intensive problem where the solution required the transmission of 160 bytes of data through the parallel network, and a communication intensive example that required the transmission of 3 Mbytes of data through the network. This data consists of solutions being sent back to the host processor and not intermediate results for another processor to work on. Studies were performed on both integer and floating-point transputers. The latter features an on-chip floating-point math unit and offers approximately an order of magnitude performance increase over the integer transputer on real valued computations. The results indicate that a minimum amount of work is required on each node per communication to achieve high network speedups (efficiencies). The floating-point processor requires approximately an order of magnitude more work per communication than the integer processor because of the floating-point unit's increased computing capacity.

Ellis, Graham K.↗

Dynamically-allocated multi-queue buffers for VLSI communication switches

Several buffer structures are discussed and compared in terms of implementation complexity, interswitch handshaking requirements, and their ability to deal with variations in traffic patterns and message lengths. A new design of buffers is presented that provide non-FIFO message handling and efficient storage allocation for variable size packets using linked lists managed by a simple on-chip controller. The new buffer design is evaluated by comparing it to several alternative designs in the context of a multistage interconnection network. The present modeling and simulations show that the new buffer outperforms alternative buffers and can thus be used to improve the performance of a wide variety of systems currently using less efficient buffers.

Tamir, Yuval↗

Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applications

With more scientific fields relying on neural networks (NNs) to process data incoming at extreme throughputs and latencies, it is crucial to develop NNs with all their parameters stored on-chip. In many of these applications, there is not enough time to go off-chip and retrieve weights. Even more so, off-chip memory such as DRAM does not have the bandwidth required to process these NNs as fast as the data is being produced (e.g., every 25 ns). As such, these extreme latency and bandwidth requirements have architectural implications for the hardware intended to run these NNs: 1) all NN parameters must fit on-chip, and 2) codesigning custom/reconfigurable logic is often required to meet these latency and bandwidth constraints. In our work, we show that many scientific NN applications must run fully on chip, in the extreme case requiring a custom chip to meet such stringent constraints.

Weng, Olivia↗

Highly Efficient Amplifier for Ka-Band Communications

An amplifier developed under a Small Business Innovation Research (SBIR) contract will have applications for both satellite and terrestrial communications. This power amplifier uses an innovative series bias arrangement of active devices to achieve over 40-percent efficiency at Ka-band frequencies with an output power of 0.66 W. The amplifier is fabricated on a 2.0- by 3.8-square millimeter chip through the use of Monolithic Microwave Integrated Circuit (MMIC) technology, and it uses state-of-the-art, Pseudomorphic High-Electron-Mobility Transistor (PHEMT) devices. Although the performance of the MMIC chip depends on these high-performance devices, the real innovations here are a unique series bias scheme, which results in a high-voltage chip supply, and careful design of the on-chip planar output stage combiner. This design concept has ramifications beyond the chip itself because it opens up the possibility of operation directly from a satellite power bus (usually 28 V) without a dc-dc converter. This will dramatically increase the overall system efficiency. Conventional microwave power amplifier designs utilize many devices all connected in parallel from the bias supply. This results in a low-bias voltage, typically 5 V, and a high bias current. With this configuration, substantial I(sup 2) R losses (current squared times resistance) may arise in the system bias-distribution network. By placing the devices in a series bias configuration, the total current is reduced, leading to reduced distribution losses. Careful design of the on-chip planar output stage power combiner is also important in minimizing losses. Using these concepts, a two-stage amplifier was designed for operation at 33 GHz and fabricated in a standard MMIC foundry process with 0.20-m PHEMT devices. Using a 20-V bias supply, the amplifier achieved efficiencies of over 40 percent with an output power of 0.66 W and a 16-dB gain over a 2-GHz bandwidth centered at 33 GHz. With a 28-V bias, a power level of 1.1 W was achieved with a 12-dB gain and a 36-percent efficiency. This represents the best reported combination of power and efficiency at this frequency. In addition to delivering excellent power and gain, this Ka-band MMIC power amplifier has an efficiency that is 10 percent greater than existing designs. The unique design offers an excellent match for spacecraft applications since the amplifier supply voltage is closely matched to the typical value of spacecraft bus voltage. These amplifiers may be used alone in applications of 1 W or less, or several may be combined or used in an array to produce moderate power, Ka-band transmitters with minimal power combining and less thermal stress owing to the combination of excellent efficiency and power output. The higher voltage operation of this design may also save mass and power because the dc-dc power converter is replaced with a simpler voltage regulator.

Source record↗

NASA’s Orbital Debris Optical Program: ES-MCAT Nearing Full Operational Capability (FOC)

The NASA JAO/ES-MCAT (Eugene Stansbery Meter Class Autonomous Telescope) Facility is nearing Full Operational Capability, or FOC. ES-MCAT is now fully capable of autonomously running all observations, including: (a) monitoring weather and closing when conditions are not safe, as well as halting observations when conditions are not suitable (e.g. too cloudy) for operations, (b) start-up/shut-down nightly tasking, (c) collecting calibration data and survey or TLE-tracked data, and (d) processing all collected data, including on-chip photometry and astrometry calibrations using the GAIA star catalogue. The processed data are then further analyzed at NASA Johnson Space Center to correlate detections with known objects in the Space Surveillance Network (SSN) catalogue. MCAT can collect data of specific objects with known orbits or can search for objects with orbits similar to those of spacecraft or rocket bodies that have recently broken up. However, the primary goal for ES-MCAT is to survey the geosynchronous (GEO) belt to provide a statistical sample of the GEO debris environment for both engineering models for spacecraft designers and long-term environment evolutionary purposes. The approach for sweeping the sky to statistically survey GEO has been investigated and updated from past surveys taken by NASA and will be reported, herein referred to as the Candy Cane method. ES-MCAT’s optical performance and the limiting magnitude for the full optical system will be discussed. An analysis used to determine which filter to use for GEO surveys (SDSS r′) includes combining the reflectivity of the primary and secondary mirrors, transmission of the field corrector and CCD window, and the quantum efficiency of the CCD detector, resulting in throughput of the full optical path. This throughput is then combined with the expected typical transparency of the atmosphere at ES-MCAT’s altitude/location for the Sloan Digital Sky Survey (SDSS) g′r′i′z′ and Johnson/Kron-Cousins BVRI filters to yield expected relative throughput.

S. M. Lederer↗

Telecom-to-visible quantum frequency converter on a silicon nitride chip

Quantum frequency conversion serves a key role in the realization of hybrid quantum networks by interfacing between wavelength-incompatible platforms. Here we present what is believed to be the first quantum frequency converter connecting visible and telecom domains on a silicon nitride (SiN) chip, using Bragg-scattering four-wave mixing to upconvert heralded single photons from 1260 to 698 nm, which covers a 192 THz span. We examine the noise sources in SiN and devise approaches to suppress noise photons at the source and target frequencies to enable measurements at the single-photon level. We demonstrate an on-chip conversion efficiency of 5% in photon flux and describe design modifications that can be implemented to significantly improve it. Our results pave the way for the implementation of complementary metal-oxide-semiconductor (CMOS)-compatible devices in quantum networks.

59 BASIC BIOLOGICAL SCIENCES↗

Energy efficient photonic memory based on electrically programmable embedded III-V/Si memristors: switches and filters

Abstract Over the past few years, extensive work on optical neural networks has been investigated in hopes of achieving orders of magnitude improvement in energy efficiency and compute density via all-optical matrix-vector multiplication. However, these solutions are limited by a lack of high-speed power power-efficient phase tuners, on-chip non-volatile memory, and a proper material platform that can heterogeneously integrate all the necessary components needed onto a single chip. We address these issues by demonstrating embedded multi-layer HfO 2 /Al 2 O 3 memristors with III-V/Si photonics which facilitate non-volatile optical functionality for a variety of devices such as Mach-Zehnder Interferometers, and (de-)interleaver filters. The Mach-Zehnder optical memristor exhibits non-volatile optical phase shifts > π with ~33 dB signal extinction while consuming 0 electrical power consumption. We demonstrate 6 non-volatile states each capable of 4 Gbps modulation. (De-) interleaver filters were demonstrated to exhibit memristive non-volatile passband transformation with full set/reset states. Time duration tests were performed on all devices and indicated non-volatility up to 24 hours and beyond. We demonstrate non-volatile III-V/Si optical memristors with large electric-field driven phase shifts and reconfigurable filters with true 0 static power consumption. As a result, co-integrated photonic memristors offer a pathway for in-memory optical computing and large-scale non-volatile photonic circuits.

Cheung, Stanley (ORCID:0000000248860013)↗

NASA Tech Briefs, August 2013

Topics covered include: Radial Internal Material Handling System (RIMS) for Circular Habitat Volumes; Conical Seat Shut-Off Valve; Impact-Actuated Digging Tool for Lunar Excavation; Flexible Mechanical Conveyors for Regolith Extraction and Transport; Remote Memory Access Protocol Target Node Intellectual Property; Soft Decision Analyzer; Distributed Prognostics and Health Management with a Wireless Network Architecture; Minimal Power Latch for Single-Slope ADCs; Bismuth Passivation Technique for High-Resolution X-Ray Detectors; High-Strength, Super-elastic Compounds; Cu-Cr-Nb-Zr Alloy for Rocket Engines and Other High-Heat- Flux Applications; Microgravity Storage Vessels and Conveying-Line Feeders for Cohesive Regolith; CRUQS: A Miniature Fine Sun Sensor for Nanosatellites; On-Chip Microfluidic Components for In Situ Analysis, Separation, and Detection of Amino Acids; Spectroscopic Determination of Trace Contaminants in High-Purity Oxygen; Method of Separating Oxygen From Spacecraft Cabin Air to Enable Extravehicular Activities; Atomic Force Microscope Mediated Chromatography; Sample Analysis at Mars Instrument Simulator; Access Control of Web- and Java-Based Applications; Tool for Automated Retrieval of Generic Event Tracks (TARGET); Bilayer Protograph Codes for Half-Duplex Relay Channels; Influence of Computational Drop Representation in LES of a Droplet-Laden Mixing Layer.

Source record↗

On-chip probabilistic inference for charged-particle tracking at the sensor edge

Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.

Das, Arghya Ranjan [Purdue U.] (ORCID:000000018451↗

CMOS photonic integrated source of broadband polarization-entangled photons

We showcase a fully on-chip CMOS-fabricated silicon photonic integrated circuit employing a bidirectionally pumped microring and polarization splitter-rotators tailored for the generation of broadband (>9 THz), high-fidelity (90–98%) polarization-entangled photons. Spanning the optical C+L-band and producing over 116 frequency-bin pairs on a 38.4-GHz-spaced grid, this source is ideal for flex-grid wavelength-multiplexed entanglement distribution in multiuser networks.

42 ENGINEERING↗

Spin Decoherence Dynamics of Er 3+ in CeO 2 Films

Developing telecom-compatible spin-photon interfaces is essential towards scalable quantum networks. Erbium ions (Er 3+ ) exhibit a unique combination of a telecom (1.5 mu m) optical transition and an effective spin-1=2 ground state, but identifying a host that enables heterogeneous device integration while preserving long optical and spin coherence remains an open challenge. In this work, we explore the potential of Er 3+ :CeO 2 films on silicon and study the Er 3+ spin coherence, offering low nuclear spin density and the potential for on-chip integration. We demonstrate a 38.8 mu s spin coherence, which can be extended to 176.4 mu s with dynamical decoupling. Pairing experiments with cluster correlation expansion calculations, we identify spectral diffusion induced by bath Er 3+ spin flip-flops as the dominant decoherence mechanism and provide pathways to millisecond-scale coherence.

36 MATERIALS SCIENCE↗

Non-resonant Bragg scattering four-wave mixing at near-visible wavelengths in low-confinement silicon nitride waveguides

Quantum state coherent frequency conversion processes—such as Bragg-scattering four-wave mixing (BSFWM)—hold promise as a flexible technique for networking heterogeneous and distant quantum systems. In this Letter, we demonstrate BSFWM within an extended (1.2-m) low-confinement silicon nitride waveguide and show that this system has the potential for near-unity frequency conversion in visible and near-visible wavelength ranges. Using sensitive classical heterodyne laser spectroscopy at low optical powers, we characterize the Kerr coefficient (∼1.55 W −1 m −1 ) and linear propagation loss (∼0.0175 dB/cm) of this non-resonant waveguide system, revealing a record-high nonlinear figure of merit (NFM = γ / α ≈ 3.85 W −1 ) for BSFWM of near-visible light in non-resonant silicon nitride waveguides. We predict how, at high yet achievable on-chip optical powers, this NFM would yield a comparatively large frequency conversion efficiency, opening the door to near-unity flexible frequency conversion without cavity enhancement and resulting bandwidth constraints.

Jaber, Nicholas (ORCID:000900070106809X)↗

NASA Tech Briefs, January 2013

Topics include: Single-Photon-Sensitive HgCdTe Avalanche Photodiode Detector; Surface-Enhanced Raman Scattering Using Silica Whispering-Gallery Mode Resonators; 3D Hail Size Distribution Interpolation/Extrapolation Algorithm; Color-Changing Sensors for Detecting the Presence of Hypergolic Fuels; Artificial Intelligence Software for Assessing Postural Stability; Transformers: Shape-Changing Space Systems Built with Robotic Textiles; Fibrillar Adhesive for Climbing Robots; Using Pre-Melted Phase Change Material to Keep Payloads in Space Warm for Hours without Power; Development of a Centrifugal Technique for the Microbial Bioburden Analysis of Freon (CFC-11); Microwave Sinterator Freeform Additive Construction System (MS-FACS); DSP/FPGA Design for a High-Speed Programmable S-Band Space Transceiver; On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers; FPGA Vision Data Architecture; Memory Circuit Fault Simulator; Ultra-Compact Transputer-Based Controller for High-Level, Multi-Axis Coordination; Regolith Advanced Surface Systems Operations Robot Excavator; Magnetically Actuated Seal; Hybrid Electrostatic/Flextensional Mirror for Lightweight, Large-Aperture, and Cryogenic Space Telescopes; System for Contributing and Discovering Derived Mission and Science Data; Remote Viewer for Maritime Robotics Software; Stackfile Database; Reachability Maps for In Situ Operations; JPL Space Telecommunications Radio System Operating Environment; RFI-SIM: RFI Simulation Package; ION Configuration Editor; Dtest Testing Software; IMPaCT - Integration of Missions, Programs, and Core Technologies; Integrated Systems Health Management (ISHM) Toolkit; Wind-Driven Wireless Networked System of Mobile Sensors for Mars Exploration; In Situ Solid Particle Generator; Analysis of the Effects of Streamwise Lift Distribution on Sonic Boom Signature; Rad-Tolerant, Thermally Stable, High-Speed Fiber-Optic Network for Harsh Environments; Towed Subsurface Optical Communications Buoy; High-Collection-Efficiency Fluorescence Detection Cell; Ultra-Compact, Superconducting Spectrometer-on-a-Chip at Submillimeter Wavelengths; UV Resonant Raman Spectrometer with Multi-Line Laser Excitation; Medicine Delivery Device with Integrated Sterilization and Detection; Ionospheric Simulation System for Satellite Observations and Global Assimilative Model Experiments - ISOGAME; Airborne Tomographic Swath Ice Sounding Processing System; flexplan: Mission Planning System for the Lunar Reconnaissance Orbiter; Estimating Torque Imparted on Spacecraft Using Telemetry; PowderSim: Lagrangian Discrete and Mesh-Free Continuum Simulation Code for Cohesive Soils; Multiple-Frame Detection of Subpixel Targets in Thermal Image Sequences; Metric Learning to Enhance Hyperspectral Image Segmentation; Basic Operational Robotics Instructional System; Sheet Membrane Spacesuit Water Membrane Evaporator; Advanced Materials and Manufacturing for Low-Cost, High-Performance Liquid Rocket Combustion Chambers; Motor Qualification for Long-Duration Mars Missions.

Source record↗

Multiplexed color centers in a silicon photonic cavity array

Entanglement distribution is central to the modular scaling of quantum processors and establishing quantum networks. Color centers with telecom-band transitions and long spin coherence times are suitable candidates for long-distance entanglement distribution. However, high-bandwidth memory-enhanced quantum communication is limited by high-yield, scalable creation of efficient spin-photon interfaces. Here, we develop a silicon photonics platform consisting of arrays of bus-coupled cavities. The coupling to a common bus waveguide enables simultaneous access to individually addressable cavity-enhanced T center arrays. We demonstrate frequency-multiplexed operation of two T centers in separate photonic crystal cavities. In addition, we investigate the cavity enhancement of a T center through hybridized modes formed between physically distant cavities. Our results show that bus-coupled arrays of cavity-enhanced color centers could enable efficient on-chip and long-distance entanglement distribution.

Komza, Lukasz↗

FPGA-Accelerated Range-Limited Molecular Dynamics

Long timescale Molecular Dynamics (MD) simulation of small molecules is crucial in drug design and basic science. To accelerate a small data set that is executed for a large number of iterations, high-efficiency is required. Recent work in this domain has demonstrated that among COTS devices only FPGA-centric clusters can scale beyond a few processors. The problem addressed here is that, as the number of on-chip processors has increased from fewer than 10 into the hundreds, previous intra-chip routing solutions are no longer viable. We find, however, that through various design innovations, high efficiency can be maintained. These include replacing the previous broadcast networks with ring-routing and then augmenting the rings with out-of-order and caching mechanisms. Others are adding a level of hierarchical filtering and memory recycling. Two novel optimized architectures emerge, together with a number of variations. These are validated, analyzed, and evaluated. We find that in the domain of interest speed-ups over GPUs are achieved. Finally, the potential impact is that this system promises to be the basis for scalable long timescale MD with commodity clusters.

97 MATHEMATICS AND COMPUTING↗

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗