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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Is random access memory random?

Most software is contructed on the assumption that the programs and data are stored in random access memory (RAM). Physical limitations on the relative speeds of processor and memory elements lead to a variety of memory organizations that match processor addressing rate with memory service rate. These include interleaved and cached memory. A very high fraction of a processor's address requests can be satified from the cache without reference to the main memory. The cache requests information from main memory in blocks that can be transferred at the full memory speed. Programmers who organize algorithms for locality can realize the highest performance from these computers.

Denning, P. J.↗
NASA NTRS1990

Analog Delta-Back-Propagation Neural-Network Circuitry

Changes in synapse weights due to circuit drifts suppressed. Proposed fully parallel analog version of electronic neural-network processor based on delta-back-propagation algorithm. Processor able to "learn" when provided with suitable combinations of inputs and enforced outputs. Includes programmable resistive memory elements (corresponding to synapses), conductances (synapse weights) adjusted during learning. Buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in layers of electronic neurons in accordance with delta-back-propagation algorithm.

Eberhart, Silvio↗
NASA NTRS1990

Porous-Floating-Gate Field-Effect Transistor

Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.

Thakoor, Anilkumar P.↗
NASA NTRS1990

Solid-state reprogrammable analog resistive devices for electronic neural networks

The fabrication and performance of WO3-based, solid-state, three-terminal device configurations as programmable analog memory elements are reported. These transistorlike device structures exhibit good resistance progammability with a remarkable resolution of a few percent of the resistive strength over a four orders of magnitude dynamic range. The most critical component of these devices is an insulating layer between the active WO3 and the cation donor layer. The progamming characteristics and operation mechanisms of the device are described, and probable reaction mechanisms critical to the device stability are discussed.

Ramesham, R.↗
NASA NTRS1992

Analog hardware for delta-backpropagation neural networks

This is a fully parallel analog backpropagation learning processor which comprises a plurality of programmable resistive memory elements serving as synapse connections whose values can be weighted during learning with buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in a plurality of neuron layers in accordance with delta-backpropagation algorithms modified so as to control weight changes due to circuit drift.

Eberhardt, Silvio P.↗
NASA NTRS2010

Modeling of Sonos Memory Cell Erase Cycle

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Phillips, Thomas A.↗
NASA NTRS2004

Hard Real-Time: C++ Versus RTSJ

In the domain of hard real-time systems, which language is better: C++ or the Real-Time Specification for Java (RTSJ)? Although ordinary Java provides a more productive programming environment than C++ due to its automatic memory management, that benefit does not apply to RTSJ when using NoHeapRealtimeThread and non-heap memory areas. As a result, RTSJ programmers must manage non-heap memory explicitly. While that's not a deterrent for veteran real-time programmers-where explicit memory management is common-the lack of certain language features in RTSJ (and Java) makes that manual memory management harder to accomplish safely than in C++. This paper illustrates the problem for practitioners in the context of moving data and managing memory in a real-time producer/consumer pattern. The relative ease of implementation and safety of the C++ programming model suggests that RTSJ has a struggle ahead in the domain of hard real-time applications, despite its other attractive features.

programming model↗
NASA NTRS1989

Manganese oxide microswitch for electronic memory based on neural networks

A solid-state, resistance tailorable, programmable-once, binary, nonvolatile memory switch based on manganese oxide thin films is reported. MnO(x) exhibits irreversible memory switching from conducting (on) to insulating (off) state, with the off and on resistance ratio of greater than 10,000. The switching mechanism is current-triggered chemical transformation of a conductive MnO(2-Delta) to an insulating Mn2O3 state. The energy required for switching is of the order of 4-20 nJ/sq micron. The low switching energy, stability of the on and off states, and tailorability of the on state resistance make these microswitches well suited as programmable binary synapses in electronic associative memories based on neural network models.

Ramesham, R.↗
NASA NTRS1989

Variable-Resistivity Material For Memory Circuits

Nonvolatile memory elements packed densely. Electrically-erasable, programmable, read-only memory matrices made with newly-synthesized organic material of variable electrical resistivity. Material, polypyrrole doped with tetracyanoquinhydrone (TCNQ), changes reversibly between insulating or higher-resistivity state and conducting or low-resistivity state. Thin film of conductive polymer separates layer of row conductors from layer of column conductors. Resistivity of film at each intersection and, therefore, resistance of memory element defined by row and column, increased or decreased by application of suitable switching voltage. Matrix circuits made with this material useful for experiments in associative electronic memories based on models of neural networks.

Nagasubramanian, Ganesan↗
NASA NTRS2011

Modeling of SONOS Memory Cell Erase Cycle

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

Phillips, Thomas A.↗
NASA NTRS2012

System and method for cognitive processing for data fusion

A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning.

Duong, Tuan A.↗
NASA NTRS1993

System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

Hall, William A.↗
NASA NTRS1987

Binary synaptic connections based on memory switching in a-Si:H for artificial neural networks

A scheme for nonvolatile associative electronic memory storage with high information storage density is proposed which is based on neural network models and which uses a matrix of two-terminal passive interconnections (synapses). It is noted that the massive parallelism in the architecture would require the ON state of a synaptic connection to be unusually weak (highly resistive). Memory switching using a-Si:H along with ballast resistors patterned from amorphous Ge-metal alloys is investigated for a binary programmable read only memory matrix. The fabrication of a 1600 synapse test array of uniform connection strengths and a-Si:H switching elements is discussed.

Thakoor, A. P.↗
NASA NTRS2011

CoNNeCT Baseband Processor Module

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Yamamoto, Clifford K↗
NASA NTRS1989

Optical pattern recognition; Proceedings of the Meeting, Los Angeles, CA, Jan. 17, 18, 1989

Papers on optical pattern recognition are presented, covering topics such as the estimation of satellite pose and motion parameters using a neural net tracker, associative memory, optical implmentation of programmable neural networks, optoelectronic neural networks, dynamic autoassociative neural memory, heteroassociative memory, bilinear pattern recognition processors, optical processing of optical correlation plane data, and a synthetic discriminant function-based nonlinear optical correlator. Other topics include an interactive optical-digital image processor, geometric transformations for video compression and human teleoperator display, quasiconformal remapping for compensation of human visual field defects, hybrid vision for automated spacecraft landing, advanced symbolic and inference optical correlation filters, and a rotationally invariant holographic tracking system. Additional topics include the detection of rotational and scale-varying objects with a programmable joint transform correlator, a single spatial light modulator binary nonlinear optical correlator, optical joint transform correlation, linear phase coefficient composite filters, and binary phase-only filters.

Liu, Hua-Kuang↗
NASA NTRS1999

SRAM Based Re-programmable FPGA for Space Applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Wang, J. J.↗
NASA NTRS1997

Radiation Effects on Current Field Programmable Technologies

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Katz, R.↗
DOE OSTI2025

Tunable shear thickening, aging, and rejuvenation in suspensions of shape-memory-endowed liquid crystalline particles

The morphological features of particles, notably shape anisotropy, critically influence the rheological properties of dense suspensions, spanning both natural and engineered systems. This work explores the potential of using shape memory particles to dynamically regulate suspension fluid flow through controllable shape transformations. First, we synthesize shape-memory particles with programmable anisotropy from liquid crystal elastomers, such that the stiffness and shapes of the particles can be tuned by manipulating temperature. Our findings reveal that suspensions from such particles exhibit significant tunability in shear thickening behavior, transitioning from discontinuous shear thickening to a Newtonian-like response within a narrow temperature range of 60 ° C. This capability to modulate rheological responses in situ presents an approach for addressing processing challenges in many applications where control over flow behavior is paramount. Furthermore, we also show that suspensions composed of these anisotropic particles can undergo physical aging, and evolve into a glassy state. This state can be escaped upon activation of the shape memory effect. This reversibility underscores the potential for using such materials to engineer systems that can enter or come out of kinetic arrest by leveraging internal mechanical responses to external stimuli. The insights gained here not only broaden our understanding of the interplay between particle geometry and suspension dynamics but also pave the way for leveraging ensembles of stimuli-responsive objects to precisely control collective behaviors in many-body systems.

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