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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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24 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Development of non-volatile semiconductor memory

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Heikkila, W. W.↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗
NASA NTRS1977

New processes and materials for ultraviolet detection with solid state devices

The three major effects that degrade external responsivity of silicon from the 1/lambda theoretical curve for a quantum detector are: surface reflectance, surface recombination, and junction depth. Since the p-n junction must be very shallow, problems relating to surface are further enhanced. MOS type of processing is necessary. HCl oxides and numerous acid clean-ups are utilized in order to obtain a contamination free surface with low Qss levels. Stringent process controls such as CV shifts, spreading resistance measurements, thickness monitoring etc., are used to analyze the surface contaminations, surface mobile charges, surface concentrations, junction depth, oxide thickness etc. Low surface concentrations of 10 to the 18th atoms/cu cm are achieved by low temperature boron nitride depositions. Shallow junction depths of the order of a few tenths of a micron are achieved by low temperature controlled diffusions. In order to improve breakdown characteristics of these shallow junction devices, field plate and deep diffused p(+) ring geometries are used.

Chopra, D.↗
NASA NTRS2007

Process for High-Rate Fabrication of Alumina Nanotemplates

An anodizing process, at an early stage of development at the time of reporting the information for this article, has shown promise as a means of fabricating alumina nanotemplates integrated with silicon wafers. Alumina nanotemplates are basically layers of alumina, typically several microns thick, in which are formed approximately regular hexagonal arrays of holes having typical diameters of the order of 10 to 100 nm. Interest in alumina nanotemplates has grown in recent years because they have been found to be useful as templates in the fabrication of nanoscale magnetic, electronic, optoelectronic, and other devices. The present anodizing process is attractive for the fabrication of alumina nanotemplates integrated with silicon wafers in two respects: (1) the process involves self-ordering of the holes; that is, the holes as formed by the process are spontaneously arranged in approximately regular hexagonal arrays; and (2) the rates of growth (that is, elongation) of the holes are high enough to make the process compatible with other processes used in the mass production of integrated circuits. In preparation for fabrication of alumina nanotemplates in this process, one first uses electron-beam evaporation to deposit thin films of titanium, followed by thin films of aluminum, on silicon wafers. Then the alumina nanotemplates are formed by anodizing the aluminum layers, as described below. In experiments in which the process was partially developed, the titanium films were 200 A thick and the aluminum films were 5 m thick. The aluminum films were oxidized to alumina, and the arrays of holes were formed by anodizing the aluminum in aqueous solutions of sulfuric and/or oxalic acid at room temperature (see figure). The diameters, spacings, and rates of growth of the holes were found to depend, variously, on the composition of the anodizing solution, the applied current, or the applied potential, as follows: In galvanostatically controlled anodizing, regardless of the chemical composition of the solution, relatively high current densities (50 to 100 mA/cm2) resulted in arrays of holes that were more nearly regular than were those formed at lower current densities. . The rates of elongation of the holes were found to depend linearly on the applied current density: the observed factor of proportionality was 1.2 (m/h)/(mA/cm2). For a given fixed current density and room temperature, the hole diameters were found to depend mainly on the chemical compositions of the anodizing solutions. The holes produced in sulfuric acid solutions were smaller than those produced in oxalic acid solutions. The arrays of holes produced in sulfuric acid were more ordered than were those produced in oxalic acid. . The breakdown voltage was found to decrease logarithmically with increasing concentration of sulfuric acid. The breakdown voltage was also found to decrease with temperature and to be accompanied by a decrease in hole diameter. The hole diameter was found to vary linearly with applied potential, with a slope of 2.1 nm/V. This slope differs from slopes (2.2 and 2.77 nm/V) reported for similar prior measurements on nanotemplates made from bulk aluminum. The differences among these slopes may be attributable to differences among impurities and defects in bulk and electron-beam-evaporated aluminum specimens.

Myung, Nosang↗
NASA NTRS2011

Active Oxidation of SiC

The high temperature oxidation of silicon carbide occurs in either a passive or active mode, depending on temperature and oxygen potential. Passive oxidation forms a protective oxide film which limits attack of the SiC:SiC(s) + 3/2 O2(g) = SiO2(s) + CO(g.) Active oxidation forms a volatile oxide and leads to extensive attack of the SiC: SiC(s) + O2(g) = SiO(g) + CO(g). The transition points and rates of active oxidation are a major issue. Previous studies are reviewed and the leading theories of passive/active transitions summarized. Comparisons are made to the active/passive transitions in pure Si, which are relatively well-understood. Critical questions remain about the difference between the active-to-passive transition and passive-to-active transition. For Si, Wagner [2] points out that the active-to-passive transition is governed by the criterion for a stable Si/SiO2 equilibria and the passive-to-active transition is governed by the decomposition of the SiO2 film. This suggests a significant oxygen potential difference between these two transitions and our experiments confirm this. For Si, the initial stages of active oxidation are characterized by the formation of SiO(g) and further oxidation to SiO2(s) as micron-sized rods, with a distinctive morphology. SiC shows significant differences. The active-to-passive and the passive-to-active transitions are close. The SiO2 rods only appear as the passive film breaks down. These differences are explained in terms of the reactions at the SiC/SiO2 interface. In order to understand the breakdown of the passive film, pre-oxidation experiments are conducted. These involve forming dense protective scales of 0.5, 1, and 2 microns and then subjecting the samples with these scales to a known active oxidation environment. Microstructural studies show that SiC/SiO2 interfacial reactions lead to a breakdown of the scale with a distinct morphology.

Jacobson, Nathan S.↗
NASA NTRS1995

Photoelectrochemical etching of silicon carbide (SiC) and its characterization

Silicon carbide (SiC) is an attractive semiconductor material for high speed, high density, and high temperature device applications due to its wide bandgap (2.2-3.2 eV), high thermal conductivity, and high breakdown electric field (4 x 10(exp 6) V/cm). An instrumental process in the fabrication of semiconductor devices is the ability to etch in a highly controlled and selective manner for direct patterning techniques. A novel technique in etching using electrochemistry is described. This procedure involves the ultraviolet (UV) lamp-assisted photoelectrochemical etching of n-type 3C- and 6H-SiC to enhance the processing capability of device structures in SiC. While under UV illumination, the samples are anodically biased in an HF based aqueous solution since SiC has photoconductive properties. In order for this method to be effective, the UV light must be able to enhance the production of holes in the SiC during the etching process thus providing larger currents with light from the photocurrents generated than those currents with no light. Otherwise dark methods would be used as in the case of p-type 3C-SiC. Experiments have shown that the I/V characteristics of the SiC-electrolyte interface reveal a minimum etch voltage of 3 V and 4 V for n- and p-type 3C-SiC, respectively. Hence it is possible for etch-stops to occur. Etch rates calculated have been as high as 0.67 micrometer/min for p-type, 1.4 micrometer/min for n-type, and 1.1 micrometer/min for pn layer. On n-type 3C- SiC, an oxide formation is present where after etching a yellowish layer corresponds to a low Si/C ratio and a white layer corresponds to a high Si/C ratio. P-type 3C-SiC shows a grayish layer. Additionally, n-type 6H-SiC shows a brown layer with a minimum etch voltage of 3 V.

Collins, D. M.↗