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At least 37 records · Page 2

"Glitch Logic" and Applications to Computing and Information Security

This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.

hardware vulnerabilities↗

From Formal Requirements to Highly Assured Software for Unmanned Aircraft Systems

Operational requirements of safety-critical systems are often written in restricted specification logics. These restricted logics are amenable to automated analysis techniques such as model-checking, but are not rich enough to express complex requirements of unmanned systems. This short paper advocates for the use of expressive logics, such as higher-order logic, to specify the complex operational requirements and safety properties of unmanned systems. These rich logics are less amenable to automation and, hence, require the use of interactive theorem proving techniques. However, these logics support the formal verification of complex requirements such as those involving the physical environment. Moreover, these logics enable validation techniques that increase con dence in the correctness of numerically intensive software. These features result in highly-assured software that may be easier to certify. The feasibility of this approach is illustrated with examples drawn for NASA's unmanned aircraft systems.

Munoz, Cesar↗

From Requirements to Autonomous Flight: An Overview of the Monitoring ICAROUS Project

The Independent Configurable Architecture for Reliable Operations of Unmanned Systems(ICAROUS) is a software architecture incorporating a set of algorithms to enable autonomous operations of unmanned aircraft applications. This paper provides an overview of Monitoring ICAROUS, a project whose objective is to provide a formal approach to generating runtime monitors for autonomous systems from requirements written in a structured natural language. This approach integrates FRET, a formal requirement elicitation and authoring tool, and Copilot, a runtime verification framework. FRET is used to specify formal requirements in structured natural language. These requirements are translated into temporal logic formulae. Copilot is then used to generate executable runtime monitors from these temporal logic specifications. The generated monitors are directly integrated into ICAROUS to perform runtime verification during flight.

Formal Methods↗

Monitoring ICAROUS: From Requirements to Autonomous Flight

The Independent Configurable Architecture for Reliable Operations of Unmanned Systems (ICAROUS) is a software architecture incorporating a set of algorithms to enable autonomous operations of unmanned aircraft applications. This paper provides an overview of Monitoring ICAROUS, a project whose objective is to provide a formal approach to generating runtime monitors for autonomous systems from requirements written in a structured natural language. This approach integrates FRET, a formal requirement elicitation and authoring tool, and Copilot, a runtime verification framework. FRET is used to specify formal requirements in structured natural language. These requirements are translated into temporal logic formulae. Copilot is then used to generate executable runtime monitors from these temporal logic specifications. The generated monitors are directly integrated into ICAROUS to perform runtime verification during flight.

Formal Methods↗

A new template for developing C++ applications in NASA's Core Flight System

In this presentation, we will demonstrate an example Core Flight System (cFS) application written in C++, compatible with the Draco releases of the Core Flight Executive (cFE) and NASA Operating System Abstraction Layer (OSAL). The application boilerplate, supporting library, and associated generation script were recently developed and licensed under the permissive Apache License 2.0 with the goal of easing the cFS app development with C++. The design and features of this application will be presented, including a higher-level interface for interactions with the cFE software bus pipes, tables, and event services. Data structures are provided for centralized telecommand and telemetry parsing which isolates bookkeeping of message components from the calling code in an application's core logic. Specific advantages of writing a cFS application in C++ will be shown, including easier avoidance of symbol collisions via namespaces, expanded compile-time checks via constant expressions, default initialization for data structures, null safety via references, improved syntax for operating on multi-dimensional arrays, and reliable serialization of enumerations via enumeration classes. Special considerations needed for integrating a C++ application will be identified, including function linkage, exceptions, and stack unwinding. Evidence for the usefulness of this template will be discussed in the context of development of a flight software application used for interfacing with a solid-state data recorder.

Dominick Allen↗

Compiler writing system detail design specification. Volume 2: Component specification

The logic modules and data structures composing the Meta-translator module are desribed. This module is responsible for the actual generation of the executable language compiler as a function of the input Meta-language. Machine definitions are also processed and are placed as encoded data on the compiler library data file. The transformation of intermediate language in target language object text is described.

Arthur, W. J.↗

Logic programming and metadata specifications

Artificial intelligence (AI) ideas and techniques are critical to the development of intelligent information systems that will be used to collect, manipulate, and retrieve the vast amounts of space data produced by 'Missions to Planet Earth.' Natural language processing, inference, and expert systems are at the core of this space application of AI. This paper presents logic programming as an AI tool that can support inference (the ability to draw conclusions from a set of complicated and interrelated facts). It reports on the use of logic programming in the study of metadata specifications for a small problem domain of airborne sensors, and the dataset characteristics and pointers that are needed for data access.

Lopez, Antonio M., Jr.↗

Automated Translation of Safety Critical Application Software Specifications into PLC Ladder Logic

The numerous benefits of automatic application code generation are widely accepted within the software engineering community. A few of these benefits include raising the abstraction level of application programming, shorter product development time, lower maintenance costs, and increased code quality and consistency. Surprisingly, code generation concepts have not yet found wide acceptance and use in the field of programmable logic controller (PLC) software development. Software engineers at the NASA Kennedy Space Center (KSC) recognized the need for PLC code generation while developing their new ground checkout and launch processing system. They developed a process and a prototype software tool that automatically translates a high-level representation or specification of safety critical application software into ladder logic that executes on a PLC. This process and tool are expected to increase the reliability of the PLC code over that which is written manually, and may even lower life-cycle costs and shorten the development schedule of the new control system at KSC. This paper examines the problem domain and discusses the process and software tool that were prototyped by the KSC software engineers.

Leucht, Kurt W.↗

Automata-Based Verification of Temporal Properties on Running Programs

This paper presents an approach to checking a running program against its Linear Temporal Logic (LTL) specifications. LTL is a widely used logic for expressing properties of programs viewed as sets of executions. Our approach consists of translating LTL formulae to finite-state automata, which are used as observers of the program behavior. The translation algorithm we propose modifies standard LTL to Buchi automata conversion techniques to generate automata that check finite program traces. The algorithm has been implemented in a tool, which has been integrated with the generic JPaX framework for runtime analysis of Java programs.

Giannakopoulou, Dimitra↗

Flight Simulator Demonstration and Certification Implications of Powertrain Failure Mitigation in a Partial Turboelectric Aircraft

The Single-aisle Turboelectric AiRCraft with Aft Boundary Layer propulsor (STARC ABL) is a concept aircraft with a partial turboelectric powertrain. The complexity and integrated nature of the partial turboelectric powertrain architecture presents failure modes and hazards not found in conventional aircraft propulsion designs. Previously, various electrical and mechanical faults and associated recovery modes were demonstrated in a dynamic model of the powertrain. It was shown that certain faults were catastrophic without recovery logic, due specifically to the interaction of the subsystems. However, in each case, the logic, known as a reversionary control mode, enabled continued operation with assumed sufficient thrust to maintain safe flight. The current work evaluates the powertrain faults and recovery strategies using a full aircraft model in a piloted flight simulator, and places it in the context of current regulatory practice. Faults initiated in flight were successfully mitigated, with the accommodated aircraft subsequently evaluated against certification requirements for three-engine aircraft, which were shown to be appropriate for the STARC-ABL configuration.

STARC-ABL↗

Flight Simulator Demonstration and Certification Implications of Powertrain Failure Mitigation in a Partial Turboelectric Aircraft

The Single-aisle Turboelectric AiRCraft with Aft Boundary Layer propulsor (STARC ABL) is a concept aircraft with a partial turboelectric powertrain. The complexity and integrated nature of the partial turboelectric powertrain architecture presents failure modes and hazards not found in conventional aircraft propulsion designs. Previously, various electrical and mechanical faults and associated recovery modes were demonstrated in a dynamic model of the powertrain. It was shown that certain faults were catastrophic without recovery logic, due specifically to the interaction of the subsystems. However, in each case, the logic, known as a reversionary control mode, enabled continued operation with assumed sufficient thrust to maintain safe flight. The current work evaluates the powertrain faults and recovery strategies using a full aircraft model in a piloted flight simulator, and places it in the context of current regulatory practice. Faults initiated in flight were successfully mitigated, with the accommodated aircraft subsequently evaluated against certification requirements for three-engine aircraft, which were shown to be appropriate for the STARC-ABL configuration.

STARC-ABL↗

Flight Simulator Demonstration and Certification Implications of Powertrain Failure Mitigation in a Partial Turboelectric Aircraft

The Single-aisle Turboelectric AiRCraft with Aft Boundary Layer propulsor (STARC ABL) is a concept aircraft with a partial turboelectric powertrain. The complexity and integrated nature of the partial turboelectric powertrain architecture presents failure modes and hazards not found in conventional aircraft propulsion designs. Previously, various electrical and mechanical faults and associated recovery modes were demonstrated in a dynamic model of the powertrain. It was shown that certain faults were catastrophic without recovery logic, due specifically to the interaction of the subsystems. However, in each case, the logic, known as a reversionary control mode, enabled continued operation with assumed sufficient thrust to maintain safe flight. The current work evaluates the powertrain faults and recovery strategies using a full aircraft model in a piloted flight simulator, and places it in the context of current regulatory practice. Faults initiated in flight were successfully mitigated, with the accommodated aircraft subsequently evaluated against certification requirements for three-engine aircraft, which were shown to be appropriate for the STARC-ABL configuration.

certification↗

AgRISTARS: Foreign commodity production forecasting. Corn/soybean decision logic development and testing

The development and testing of an analysis procedure which was developed to improve the consistency and objectively of crop identification using Landsat data is described. The procedure was developed to identify corn and soybean crops in the U.S. corn belt region. The procedure consists of a series of decision points arranged in a tree-like structure, the branches of which lead an analyst to crop labels. The specific decision logic is designed to maximize the objectively of the identification process and to promote the possibility of future automation. Significant results are summarized.

Dailey, C. L.↗

Display of scientific data structures for algorithm visualization

We present a technique for defining graphical depictions for all the data types defined in an algorithm. The ability to display arbitrary combinations of an algorithm's data objects in a common frame of reference, coupled with interactive control of algorithm execution, provides a powerful way to understand algorithm behavior. Type definitions are constrained so that all primitive values occurring in data objects are assigned scalar types. A graphical display, including user interaction with the display, is modeled by a special data type. Mappings from the scalar types into the display model type provide a simple user interface for controlling how all data types are depicted, without the need for type-specific graphics logic.

Hibbard, William↗

Quantum metrology

This paper addresses the formal equivalence between the Mach-Zehnder interferometer, the Ramsey spectroscope, and a specific quantum logical gate. Based on this equivalence we introduce the quantum Rosetta Stone, and we describe a projective measurement scheme for generating the desired correlations between the interferometric input states in order to achieve Heisenberg-limited sensitivity.

quantum interferometry lithography projective meas↗

High-Performance Wireless Telemetry

Prior technology for machinery data acquisition used slip rings, FM radio communication, or non-real-time digital communication. Slip rings are often noisy, require much space that may not be available, and require access to the shaft, which may not be possible. FM radio is not accurate or stable, and is limited in the number of channels, often with channel crosstalk, and intermittent as the shaft rotates. Non-real-time digital communication is very popular, but complex, with long development time, and objections from users who need continuous waveforms from many channels. This innovation extends the amount of information conveyed from a rotating machine to a data acquisition system while keeping the development time short and keeping the rotating electronics simple, compact, stable, and rugged. The data are all real time. The product of the number of channels, times the bit resolution, times the update rate, gives a data rate higher than available by older methods. The telemetry system consists of a data-receiving rack that supplies magnetically coupled power to a rotating instrument amplifier ring in the machine being monitored. The ring digitizes the data and magnetically couples the data back to the rack, where it is made available. The transformer is generally a ring positioned around the axis of rotation with one side of the transformer free to rotate and the other side held stationary. The windings are laid in the ring; this gives the data immunity to any rotation that may occur. A medium-frequency sine-wave power source in a rack supplies power through a cable to a rotating ring transformer that passes the power on to a rotating set of electronics. The electronics power a set of up to 40 sensors and provides instrument amplifiers for the sensors. The outputs from the amplifiers are filtered and multiplexed into a serial ADC. The output from the ADC is connected to another rotating ring transformer that conveys the serial data from the rotating section to the stationary section. From there, a cable conveys the serial data to the remote rack, where it is reconditioned to logic level specifications, de-serialized, and converted back to analog. In the rotating electronics are code generators to indicate the beginning of files for data synchronization.

Griebeler, Elmer↗

Improved Autoassociative Neural Networks

Improved autoassociative neural networks, denoted nexi, have been proposed for use in controlling autonomous robots, including mobile exploratory robots of the biomorphic type. In comparison with conventional autoassociative neural networks, nexi would be more complex but more capable in that they could be trained to do more complex tasks. A nexus would use bit weights and simple arithmetic in a manner that would enable training and operation without a central processing unit, programs, weight registers, or large amounts of memory. Only a relatively small amount of memory (to hold the bit weights) and a simple logic application- specific integrated circuit would be needed. A description of autoassociative neural networks is prerequisite to a meaningful description of a nexus. An autoassociative network is a set of neurons that are completely connected in the sense that each neuron receives input from, and sends output to, all the other neurons. (In some instantiations, a neuron could also send output back to its own input terminal.) The state of a neuron is completely determined by the inner product of its inputs with weights associated with its input channel. Setting the weights sets the behavior of the network. The neurons of an autoassociative network are usually regarded as comprising a row or vector. Time is a quantized phenomenon for most autoassociative networks in the sense that time proceeds in discrete steps. At each time step, the row of neurons forms a pattern: some neurons are firing, some are not. Hence, the current state of an autoassociative network can be described with a single binary vector. As time goes by, the network changes the vector. Autoassociative networks move vectors over hyperspace landscapes of possibilities.

Hand, Charles↗